【作者】 李炜；

【导师】 毛陆虹；

【作者基本信息】 天津大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 本论文设计了一个电荷泵锁相环电路,研究了其相位噪声特性并对该锁相环进行了详细的模拟。该锁相环主要用于MCU中的时钟产生模块,其输出的时钟信号占空比为50%,频率为128MHz,最高频率可以达到192MHz,可以满足在高速MCU系列集成电路的要求。设计中采用了自顶向下的方法,对电荷泵锁相环电路从系统级开始研究,逐步过渡到晶体管级的模块的设计。首先,应用Matlab数学工具以及VerilogA语言建立了锁相环系统的数学模型和行为级模型,对环路参数进行了优化。其次,在确定了模块的指标后,对每一个模块进行了详细的设计与模拟,包括基准源,相位频率探测器(PFD),电荷泵(Charge Pump),低通滤波器(LPF),电压控制振荡器(VCO)和分频器(Divider)。然后,将模块组合成为系统后,分析了系统在不同的工艺、温度和电源电压下的工作情况,从模拟结果可以看出,各个模块以及整体锁相环电路的设计均达到了设计要求。最后,完成了版图的绘制与验证工作并已交付Foundry进行流片。另一方面,本论文还对VCO以及锁相环系统相位噪声的基本理论进行了深入的研究,利用Hajimiri提出的VCO的相位噪声模型进行了预测,并与模拟结果进行了对比分析,此外还应用了周期性小信号的分析方法对锁相环系统的相位噪声进行了模拟与分析。本论文的研究成果对于锁相环电路中的模块级设计与系统级设计,尤其是相位噪声的分析与模拟均有很好的指导意义和参考价值。更多还原

【Abstract】 This paper is focused on the design of a Charge Pump PLL (Phase Locked Loop)and the researching of PLL’s phase noise characteristic, and then the PLL circuit issimulated in detail. The charge pump PLL is mainly used for clock generator modulein MCU, whose output clock signal is 50% duty cycle, output frequency of 128MHzand maximum output frequency is 192MHz. These specifications can meet therequirements of high speed MCU integrated circuits.The design method of Top to Down is used, which is from the system leveldesign of charge pump PLL to the transistor level design of each block in PLL. Firstly,the mathematic model of PLL is built by Matlab and the behavior model is built byVerilogA language. Then the loop parameters are optimized by these models.Secondly, after each block’s specification is decided, detailed design and simulation ofthese blocks are completed including Phase Frequency Detector (PFD), Charge Pump,Low Pass Filter (LPF), Voltage Controlled Oscillator (VCO) and Divider. Thirdly, thecharge pump PLL system consisted by these blocks is simulated under differentprocess, temperature and power voltage. From the simulation results, each block andthe whole PLL system have obtained the design specifications. Finally, layout andverification of the PLL circuit are completed and the PLL circuit has been taped out.On the other hand, in the paper VCO and PLL system’s phase noise theory andcharacteristic have been deeply researched. VCO’s phase noise is predicted byHajimiri’s phase noise model and compared with the simulation result. Furthermore,phase noise of the PLL system is simulated and analyzed by PSS (Periodic SmallSignal) method.The achievement of this paper will provide lots of useful guides and referenceson the design of system and module level in PLL circuit, especially on the analysisand simulation of phase noise.更多还原