【作者】 孙缵；

【导师】 邹雪城；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2005， 硕士

【摘要】 液晶显示器以其轻薄短小、低耗电量、无辐射危险,平面直角显示以及影像稳定不闪烁等优势,在图像显示领域获得了越来越广泛的应用,这就势必引发与之配套的驱动控制芯片的广泛研究和开发。本文设计了一种新型的应用于128×129 像素的STN LCD 驱动控制芯片,它支持多种主流MPU 接口,内嵌时序控制电路、电源电路以及32K 的SRAM,采用帧速率控制和脉宽调制方法实现4 级灰度,为图像点阵液晶显示应用提供了完美的解决方案。根据自顶向下的设计思想,将芯片进行层次化功能划分,同时参考已有的同类驱动芯片的设计经验,结合原理图输入方法对部分模块进行设计,最后根据系统设计的框架对各模块进行协调设计,并进行芯片的整体功能验证,从而完成芯片的前端设计。本文研究的重点在于STN LCD 驱动控制芯片的总体设计方案,并就其中的接口电路、时序控制电路、FRC/PWM 调制电路、驱动电路、电源电路以及SRAM 模块和振荡器等电路的设计作了详细的描述。在设计的过程中,采用Verilog 硬件描述语言和Modelsim 仿真工具对电路中数字部分的逻辑功能与时序关系进行了仿真验证; 基于chartered 的0.35um CMOS 高压工艺,采用Spice 仿真软件Spectre 对电路中模拟部分的功能进行了仿真验证。同时,在设计的各个层次,结合使用了功耗管理、门控时钟、总线隔离等多种流行的低功耗设计技术,十分有效的降低了芯片正常工作模式的功耗。在完成芯片的数模混合仿真、版图设计和后仿真以后,便可以进行试流片。更多还原

【Abstract】 For its advantages of portability, mini bulk, low power, non-radiation danger, flat display and steady image, LCD (Liquid Crystal Display) has been more and more widely used in the field of image display, which certainly will induce extensive research and development of LCD driver & controller. In this paper, the design of a novel STN LCD driver & controller IC with 128×129 pixels is demonstrated. This chip not only supports many mainstream MPU interface, but also integrates timing control circuit, power supply circuit and 32Kbits SRAM, and combines frame rate control & pulse width modulation method to realize 4-level gray scale. So it provides an ideal scheme for graphic dot-matrix LCD systems. Based on the “Top-to-down”methodology, the hierarchy partition from top behavioral level to bottom functional blocks had been framed. Meanwhile, the direct schematic design of some subcircuits had also been conducted in reference to other function-like circuits. Besides, the whole chip simulation and verification were conducted to examine the matching between the design and the requirements of specification. Then, completed the front-end design. The paper puts emphasis on the whole design of this LCD driver & controller. Some key modules are discussed in great detail, incluing interface circuit, timing control circuit, FRC/PWM function circuit, power supply circuit, drive circuit, Oscillator, and so on. Based on chartered 0.35um CMOS high voltage technology, Verilog HDL、Modelsim and Spectre simulator are used to verify function and timing of our design met with the initial specification. At the same time, multiple popular low power technologies, such as Dynamic Power Management, Gated clock, Bus-separation, are used in different design levels, which reduced the chip’s power consumption remarkably. After completed mixed-signal simulation, layout design and post-layout verification, the chip can be tape out.更多还原