【作者】 颜伟成；

【导师】 沈绪榜； 陈朝阳；

【作者基本信息】 华中科技大学 ， 模式识别与智能系统， 2005， 硕士

【摘要】 数字音视频编解码标准是数字音视频产业的共性基础标准,具有巨大的产业需求。新世纪以来,随着编解码技术本身的进步和芯片集成度、计算速度实现条件的发展,数字音视频编解码技术标准面临更新换代的历史性机遇。我国牵头制定的数字音视频编解码技术标准AVS(Audio Video coding Standard)代表了当前的国际先进水平。AVS 高清晰解码芯片的实现,是AVS 产业化的重要里程碑,对我国数字电视以及数字音视频产业的发展具有基础意义。本文的研究目标是解决视频解码芯片核的系统接口以及验证问题,包括码流输入接口,帧存取接口,以及音视频输出接口等,分别对应于PCI 局部总线接口,DDR SDRAM 接口,I2C, I2S,CCIR/SMPTE 等接口。由于我们的FPGA 开发环境的要求,PCI 总线接口采用了PLX 公司的PCI90XX 系列的接口,因此PCI 总线接口一侧转换为PLX 局部总线接口的设计。I2C 接口是用来对AD 公司的TV Encoder 芯片AD7311 进行编程的,因此本文还讨论了I2C 控制器的设计。测试和物理设计阶段是整个IC 设计流程中不可缺少的部分,本文就芯片的可测试性问题和后端设计流程也进行了研究。文中所提到的设计在Xilinx 公司的VirtexII Pro 型号FPGA 上得到功能验证,并应用在AVS101 芯片中,流片后经测试功能正常且满足要求。更多还原

【Abstract】 As the common base standard in digital audio and video industry, the digital audio video coding standard has a great amount of requirements in information industry. Since the start of this new century, with the great progress made in technology of encoding and decoding and the rapid development in IC and computing technology, the digital audio video coding standard is facing with a historic opportunity. The AVS(Audio Video Coding Standard) standards for the current world advanced level. The implementation of AVS101-a high definition decoder chip is a import milestone of the industrialization of AVS and is very significant to the development of video audio industry. The main object of this thesis is to resolve the Peripheral Interface of the Decoder core and its verification, including the stream input/output interface, frame access interface and AV interface etc., which are PCI local bus interface , DDR SDRAM interface, I2C, I2S, CCIR/SMPTE interface respectively. Because of the constraints of our FPGA development environment, we design the PCI90xx local bus interface to match the PCI90xx-serial PCI-bridge chip in out FPGA development board. The I2C interface is used to control the video encoder chip-ADV7311.The design of I2C master interface is also covered in this thesis. DFT(Design For Test) and physical design are also introduced in this thesis. The design mentioned in this thesis has been functional verified in a XILINX FPGA(Virtex II Pro VP100) and successfully taped out in SMIC.更多还原