集成电路超深亚微米互连效应与物理设计研究

【作者】 薛振华；

【导师】 李惠军；

【作者基本信息】 山东大学 ， 信号与信息处理， 2005， 硕士

【摘要】 集成电路特征尺寸进入超深亚微米级,使得芯片速度更快、功耗更低、芯片整体功能更强,且成本更低。然而,随之而来的串扰(crosstalk)效应、天线(antenna)效应,以及IR压降等互连效应问题也成为后端设计的瓶颈,制约着集成电路的发展。新的工具、方法、和设计流程对于设计的成功越来越重要。 本课题根据集成电路超深亚微米物理设计与优化的技术要求,以新的工具、方法和设计流程为依托,旨在对超深亚微米层次下的所出现的信号完整性及物理设计中所出现的热点问题进行探索和研究。 首先,该研究着眼于当代物理设计的发展,基于超深亚微米互连特性、信号完整性等技术关键,对影响信号完整性的主要互连效应及其抑制方案进行了系统的研究;对超深亚微米物理设计的技术路线进行了深入的探讨。 其次,在此基础上,对物理设计流程中的热点问题,诸如:高性能时钟布线、布图规划、布局布线、电源分布网络的设计与优化及寄生参数的提取等,进行了较为深入的研究。 基于上述诸多项研究成果,确定了合理的技术路线及设计与优化流程。运用Synopsys超深亚微米级物理设计软件,实现了32位RISC CPU的物理级设计。该设计采用拥挤与时序双重驱动模式,有效的满足了可布线性与时序功能的要求。在设计流程中,进行了布局内优化、布线优化、搜索提炼、搜索修补、可制造性优化等多重分步优化方式,显著提高了设计质量。 本项研究针对影响超深亚微米物理设计的主要技术难点信号完整性问题,在提高电源规划质量的同时,分别对串扰效应和天线效应进行了相应的抑制。设计中,笔者成功地实现了布局后优化和布线阶段对串扰效应的抑制设计,进行了布线后的详细分析,完成了对残存的违规连线的完全修补。此外,在详细布线后,通过设定天线规则,采用高层跳线方式修补了违规设计,消除了天线效应,避免了低层跳线的昂贵代价。 本论文对超深亚微米信号完整性和物理设计流程所进行的深入研究,对当代超大规模集成电路物理级设计与优化具有一定的创新性意义。更多还原

【Abstract】 As the integrated circuits (IC) are scaled into very deep submicrometer (VDSM) dimensions, chip operates much faster and more powerful with lower power and cost. However, crosstalk, antenna and IR drop become the bottle-neck of the physical design, which restrain the development of IC. New CAD tools, methods and design flow become more and more important for the success of design.Based on the technological requirement of VDSM physical design and optimization, supported by new CAD tools, methods and design flow, this topic aimed to explore and research the SI (single integrate) and the hot problems in physical design under VDSM technology.First, focused on the development of modem physical design and based on the key technique of VDSM interconnect characteristics, SI and so on, the author has a systematic and deep research on the VDSM physical design and the cooling scheme of the interconnect effects, which affect the SI.Second, based on the first point, the author has a deep research on hot problems in physical design flow such as high powerful clock routing, floorplan, place and route, power plan and optimization, parastic extraction and so on.Based on the above results, the author has established proper design and optimization flow and completed the physical design of a 32 bits RISC CPU by the VDSM CAD tools of Synopsys. This design adopted the mode of congest-driven and timing-driver and effectively meet the requirement of routing and timing. Besides, the design also adopted the optimization means such as in-placement optimization, routing optimization, search and refine, search and repair, DFM optimization and so on and greatly improved the quality of design.As for the SI which is the main problem for VDSM physical design, the design offers a correspondent restraint to crosstalk and antenna while improving power plan. During the design, the author has successfully restrained the crosstalk in post-placement optimization and routing, has had detailed analysis for crosstalk after (?)cating and has completed the repair for remained violations. Besides, by setting theantenna rule and fixing antenna violations by breaking the antenna with a higher-layer metal, the author has deleted the antenna effect and avoided the high cost from top-layer metal to lower-layer metals.The deep research on VDSM SI and the physical design flow has a creative significance on modern VLSI IC physical design and optimization.更多还原