【作者】 付昱；

【导师】 高明伦；

【作者基本信息】 合肥工业大学 ， 计算机软件与理论， 2005， 硕士

【摘要】 基于IP重用的SoC设计技术的应用和推广不仅可以极大的降低整个系统的开发费用,缩短产品面市时间,还能在原有芯片的基础上增加更多功能,从而提高设计效率,促进整个集成电路的发展。如今,SoC技术已经成为集成电路产业中主流技术之一。 片上互连通讯与SoC测试是其中两项关键技术。一方面,片上总线是目前广泛应用的IP核互连方案,基于总线的片上通讯设计在SoC设计技术中占有重要地位。另一方面,随着芯片的日益复杂,使得对芯片的测试越来越困难,所以在芯片早期设计阶段,加入可测试结构就变的比较重要。基于边界扫描的SoC测试技术也有较为成熟的研究。 本文以8位SoC平台为载体,研究SoC的片上总线技术以及边界扫描技术(JTAG)。所使用的处理器核是合肥工业大学微电子设计研究所自主知识产权的8位RISC MCU软核——HGD08R01。基于该软核特点设计出片上总线,搭建SoC平台。在此基础上研究其中一个IP模块——JTAG模块及相关应用。完成的工作包括: 1.8位SoC平台的片上总线结构及总线协议研究 2.基于8位SoC平台的JTAG模块总体结构设计; 3.JTAG模块各子模块的设计,包括JTAG核心模块、指令寄存器模块、数据选择模块和设备识别寄存器模块; 4.利用基于仿真的功能验证方法,完成对JTAG模块的RTL级验证。 本论文完成了8位SoC平台片上总线结构的设计和JTAG模块设计和实现,并研究了JTAG模块的多种应用,为SoC平台设计和边界扫描技术的研究与应用积累了经验。更多还原

【Abstract】 The Intellectual Properties (IP) reuse based System on Chip (SoC) design technology has been widely used in the Integrated Circuit (IC) industry. It can not only significantly reduce the Time to Market (TTM) and the system cost, but also allow to integrate more functions and to improve the IC design productivity. It has become one of the mainstream technology in the industry now days.SoC interconnection architecture and SoC testing are two of the most important technologies. As to the former, the bus based communication architecture has been popularly used in SoC design. In the context of SoC testing, with the chips becoming more and more complex, it becomes more and more important to design SoC testing in the early stage of the design process. The studies on the boundary scan based SoC testing technology turn out to be relatively mature.In this thesis, we study these two technologies in an 8-bit SoC platform, where the MCU soft core IP called HGD08R01 was designed by the VLSI institute of Hefei University of Technology. We first designed a bus protocol based HGD08R01, and then designed various peripheral IP to establish this SoC platform. The JTAG module was one of such IPs. The main contribution of the study is summarized as follows.1. Designing the on chip bus architecture and protocols in the 8-bit SoC platform;2. Designing the JTAG IP module for the platform, including the JTAG top-level architecture design, sub-module design and functional verification of JTAG.更多还原