【作者】 李漓；

【导师】 王泽毅；

【作者基本信息】 清华大学 ， 计算机软件与理论， 2004， 硕士

【摘要】 集成电路特征尺寸的急剧缩小、工作频率的不断提高已使互连寄生效应成为影响VLSI电路性能的主要因素[1]。在GHz以上纳米级数字与数-模混合电路中,为了高精度的时延和串扰分析,需要快速准确地计算金属连线间的耦合寄生电容,这使得提取所有导体间的全耦合电容矩阵变得越发重要。近几年来,全耦合电容矩阵计算的一些初步探索已经逐步展开,如宏模型和区域分解等。最近,本课题组基于直接边界元法提出一种三维全局电容矩阵提取方法——层次式块边界元法(Hierarchical Block Boundary Element Method, HBBEM)[2],其通过计算小规模三维块的边界电容矩阵(Boundary capacitance matrix, BCM)和层次式合并算法,大大减少了提取电容矩阵的计算量。基于论文[2]提出的层次式块边界元法,本文做了以下多项改进:提出三维BEM子块的多层混合切割方法,使各BEM子块之间的交界面更小,从整体上提高了层次式合并算法的速度。提出边界元非均匀划分方法,可根据不同介质层具有不同线宽和线间距的特点,作有效的边界元非均匀划分,提高了对BEM子块的BCM进行计算与合并的速度,尤其适合于对数-模混合电路的提取。将BCM计算的复用推广到所有的BEM叶子块上,允许其中包含任意数目和形状的导体。改进了层次式计算的流程,使算法的空间复杂度降到原算法的1/5左右。本文所述各项算法均已实现于全耦合电容提取程序HBBEM中。对若干实际数-模混合电路版图的计算结果表明,跟论文[2]所实现的程序原型HBBEM相比,改进后HBBEM的速度可提高一倍以上,并且精度有显著改善;在计算含多层布线介质且线宽、线间距变化剧烈的模拟集成电路时,对精度的改善尤其突出。大量数值结果表明,改进的HBBEM在提高算法的适应性与稳定性方面达到了很好的效果,能够较好适应多层实际数-模混合电路的模拟需要。更多还原

【Abstract】 With the feature size scaled down and work frequency increased, the parasitic parameters of interconnects have become dominant influencing the performance of VLSI circuits. For the timing verification with high precision, fast and accurate capacitance extraction of interconnects is required, especially in the current design of nano-scale integrated circuits with frequency above several GHz. This also improves the importance to extract the full coupling capacitance matrix of interconnects.In the recent years, some preliminary researches were carried out about the global computation based on the direct boundary element methods, such as the Macro-Model computation and zone partition method. Recently, our group proposed a new global method - Hierarchical Block Boundary Element Method (Hierarchical Block BEM) for 3-D interconnect capacitance extraction. This method is based on direct BEM and improves the computational efficiency greatly by transforming a large-scale problem into some small-scale problems and the reuse of computation.Based on the Hierarchical block BEM, this dissertation has made some improvement as following:A mixed partition strategy for 3-D BEM blocks is proposed. That makes the interfaces between blocks smaller. Therefore the efficiency of combination process is improved as a whole.An efficient nonuniform partition of boundary elements are proposed to adapt the character of interconnects in analog integrated circuit. That speeds up the computation of each leaf BEM block and combination of neighbor BEM blocks.A new reuse technology is proposed, which expand the reuse of BEM block computation into all of leaf BEM blocks, no mater how much <WP=5>and how complex the conductors in them are.The algorithm organization is improved. That reduces the space complexity to about 1/5 of before.All the above approaches have been implemented in the capacitance extraction program "HBBEM". The numerical results of several testing cases and real analog integrated circuit layout show that the improved HBBEM is about two times faster than the original HBBEM[2], with higher accuracy as well. Furthermore, more numerical results show that the adaptability and stability of HBBEM is improved much. Those make the improved HBBEM fit for the need of analog stimulation of real VSLI circuit.更多还原