【作者】 刘杰；

【导师】 梁华国；

【作者基本信息】 合肥工业大学 ， 计算机应用技术， 2004， 硕士

【摘要】 科技的发展，电子技术的应用，推动了电子产品的研发，引起了电子设计自动化的提高，出现了大规模集成电路和片上系统(SOC)。由于专用集成电路设计成本高，周期长，而可编程逻辑器件(PLD)易于设计，周期短，可再利用，因此可编程逻辑器件得到了迅猛发展，不仅集成规模被提高，而且可以作为SOC的内核IP使用。随之而来的便是器件的质量问题。如何检测PLD的质量，确定其成品率已成为当务之急，与电路功能设计一起确立为电子设计中的两大主题。 本论文紧跟科技发展动向，主要研究了基于与或阵列结构的PLD的可测性设计问题。首先从PLD的基本单元着手，研究分析了已有的关于与或阵列的可测性问题，总结出四种可测性设计方案，即使用特殊编码的并发性可测性设计，采用奇偶检测器的可测性设计，进行特征值分析的可测性设计以及分块可测性设计，并介绍了PLD中的边界扫描技术。随后，论文介绍了一种自行研究的基于末端倒置、纵向观测的与或阵列可测性设计方案。这种方案根据电路的结构特点，采用了一种特殊处理办法，在测试状态下，可以把电路的原始输出端当作输入端使用，并在电路内部的乘积线端接入异或门，对测试结果进行压缩。经过各种方案对比及应用条件分析，得出结论：此方案在保证高故障检测覆盖率的情况下，不仅使用通用测试集，减少测试矢量数，还大大节约了附加硬件开销，特别适合于大规模PLD的内测试设计。最后，论文就大规模PLD的内测试设计提出了指导性设计方案：采用基于末端倒置、纵向观测的可测性设计方案处理与或阵列测试、采用扫描通路技术实施内部触发器测试。并讨论了有无边界扫描电路下的测试矢量产生、施加，及测试结果响应。 新的基于末端倒置、纵向观测的与或阵列可测性设计方案的提出，及大规模PLD内测试设计的讨论为PLD的研发、应用和推广注入了强大的动力，必将引起PLD量和质的更上一层。更多还原

【Abstract】 With science and technology development and electronic technique applications, the research and development of electronic product have been promoted, and electronic design automation has been improved.So there appear Large Scale Integrated Circuits (LSICs) and Systems on Chip(SoC). Because the design cost of Application Specific Integrated Circuit(ASIC) is very high and the time of its design is very long, and yet Programmable Logic devices(PLDs) are designed easily, design time short, and they can be recycled. PLDs have been swiftly and violently developed. Their integrated scales have been enhanced, and they may be made into intellectual propertys (IP) of SoC. And then the product qualities cause more attention. How to examine the quality of PLDs and to make certain the quotiety of finished product have become urgent affairs, and have been established into two large research tasks in the electronic design with the circuit function design.Hard following science and technology development, the thesis focuses on the testable design of PLDs with AND-OR arrays. At first, the known testable design schemes of AND-OR arrays are studied and analysed, and four schemes of testable design have been gained, namely, the concurrent testable design of using special coding, the testable design of using parity checking, the testable design of signature analysis, and the divide-and-conquer testable design. At the same time the technique of boundary scan in PLDs is introduced too. Second, a new-style testable design scheme for AND-OR arrays is introduced based on output-inversion and portrait-observation. The scheme adopts a special disposal method by the structure characteristics of PLDs, which, in the test mode, may regard the original outputs as inputs, and compress the test results by jointing cascades of XOR gates at the portions of the product lines. The analysis of all test techniques and their application conditions results in the conclusion that the scheme does not only use a universal test set and decrease the number of test, but also abundantly reduce area overhead in ensuring high fault coverage, and especially fit for the built-in test design of very large scale PLDs. At last, the steering design schemes for the built-in self-test design of very large scale PLD are brought forward: testing AND-ORarrays by using the scheme based on output-inversion and portrait-observation; testing interior flip-flop by adopting the scan path technique. More over,the generation and infliction of the test pattern and the response of the test result with or without boundary scan circuits are discussed.The proposal of a new-style testable design scheme based on output-inversion and portrait-observation for AND-OR arrays and the discussion of the built-in self-test of very large scale PLDs provide tremendous motivation for the research, application and spread of PLDs. As a result,PLDs will be enhanced in the quantity and the quality.更多还原