【作者】 李飞宇；

【导师】 颜永红；

【作者基本信息】 湖南大学 ， 微电子学与固体电子学， 2004， 硕士

【摘要】 随着光纤网络的发展，网络的带宽己达到了吉比特，在今后几年很快就要达到10吉比特甚至数十吉比特。大量事实表明，高速网络中限制终端用户到终端用户之间的瓶颈在于，对网络中TCP流的中止。由于网络终端中的主CPU是一个通用部件，处理协议的能力不强。为了使终端用户能够充分享受广阔带宽资源，要将TCP数据流的处理从主CPU中卸载出来，用专门针对TCP协议处理的ASIC来实现。本文中实现了TCP数据流重组与交付的ASIC前端设计。 首先，根据TCP协议的特点，确定协议处理器的体系结构并进行功能模块划分。该协议处理器中可以容纳三个TCP连接，它由三个连接模块和这三个连接模块所共用的输入状态机、寄存器堆和连接管理模块组成。每个连接模块又包含六个子模块，分别为宏状态机、数据错位模块、存储器、写存储器的控制器、数据包过滤模块和指针产生模块。 在划分功能模块后，用硬件描述语言Verilog-HDL对各模块进行RTL级描述。用ADLC公司的仿真器Active-HDL6.1建立测试平台，验证协议处理器的RTL级模型。 随后，使用Synopsys公司的Design Compiler逻辑综合工具和UMC0.18um的工艺库，把RTL级的协议处理器转换成带有物理信息的门级电路网表。并提取出门级网表的Verilog文件和延时信息文件，在Mentor Graphics公司的仿真器ModelSim SE PLUS 5.8中进行门级电路仿真。验证门级网表形式协议处理器功能的正确性。 最后，为了分析协议处理器中所有路径延时的正确性，用静态时序分析工具Prime Time进行分析。综合分析表明：协议处理器时钟频率可以达到100M，处理TCP数据流的能力可以达到3.2 Gbit网络的线速度。 该协议处理器的设计将原来通过软件方式处理的TCP协议卸载到ASIC上完成，将应用程序与网络分离处理，使终端用户能够享受充分广阔的带宽资源。为我国开发自主知识产权的高层协议芯片提供了坚实的技术基础。更多还原

【Abstract】 The band width of network has reached Gbit, with the development of fiber network, and it will reach 10 Gbit even more. It has been proved by a lot of facts that the bottle-neck from end to end in high-speed network is the termination of TCP-stream. Terminal CPU is a generic component, whose efficiency of process TCP protocol is low. In order that the end-user can take advantage of the vastitude band resource, the process of TCP-stream must be offloaded from host-CPU to ASIC. This paper introduces the fore-design of this ASIC.At first, I frame the architecture of the processor, and plot out function module according to the protocol’s characteristic. It makes up of input-fsm module, register-file module, link-supervise module and three connection module, and each connection sub-module contain six module, such as macro-fsm module, data-slip module, the controller of memory access module, packet filter module, generation-point module and memory.Secondly, contrive each module in Verilog-HDL, and validate the RTL-processor by ADLC’s emulator Active-HDL 6.1Thirdly, synthesize the design by Synopsys’s Design Compiler, convert the RTL-module to gate-level netlist. Then distill the Verilog file and time-delay file from this netlist by DC, and validate the gate-level netlist in Mentor Graphics’ emulator ModelSimSE PLUS 5.8.At last, validate all path’s scheduling in Synopsys’s static scheduling analysis tool Prime Time, and the result indicate that processor’s clock frequency may attain 100MHZ. the ability of process TCP-stream achieves the 3.2Gbit network’s wire-speed.The processor offloads the task accomplished by software from host CPU to ASIC, and separates the application and network, and makes the end-user make full use of the abundance band. The development of this processor provide stability base for our country to develop the intellect self-determination high layer chip.更多还原