【作者】 史进；

【导师】 陈培毅；

【作者基本信息】 清华大学 ， 微电子学与固体电子学， 2001， 硕士

【摘要】 本论文主要介绍的是基于SOI技术的SiGe异质结MOS器件。 与体Si器件相比, 采用SiGe材料的异质结器件已经在许多方面显示出了强大的优势:譬如更大的载流子迁移率，更大的跨导，更强的电流驱动能力以及更快的电路速度等等。在论文中我们给出了两种不同的材料结构来与体Si材料进行比较，用应变的Si Cap层和弛豫的SiGe材料层构建NMOS管，用弛豫的Si Cap层和应变的SiGe材料层构建PMOS管。通过比较实验我们可以获知, 应变Si材料中的电子迁移率相比于体Si材料最大可有48.5%的提高，而应变SiGe材料中的空穴迁移率相比于体Si材料可有近15%的提高。论文的第二部分介绍了SOI器件的优点: 无latch-up效应， 较低的源漏寄生电容以很容易形成浅结等，并对具体的机理作出了相应的解释。之后我们研究了SOI MOSFET的BMHMT工作模式，同时介绍了这种工作模式的优点: 驱动电流大,可替代BICMOS电路中的三极晶体管实现BICMOS电路。除了理论上的探究和了解，本文就具体的设计问题，包括器件结构设计，版图设计以及工艺参数设计都进行了详细的讨论，并对流水问题中遇到的一些反常现象作出了理论上的推测以及模拟层次上的验证。最后，我们基于Silvaco软件模拟并调节了杂质注入的能量和剂量，并结合实验结果调整了PMOS管和NMOS管的阈值电压，制备出了合格的BMHMT工作模式的SOI异质结MOSFET单管。针对具体的材料结构, 我们还对UHV/CVD设备生长的SiGe材料进行了DCXRD， TEM， SIMS和AFM测试及分析。更多还原

【Abstract】 This article is mainly about the SiGe hetrojunction MOS device fabricated by SOI technology. The hetrojunction device fabricated with SiGe material has shown great advantages over bulk sample in many aspects: higher carrier mobility, larger transconductance, stronger drive capability and hence faster circuit speed. Here we take the strained Si cap layer with relaxed SiGe layer grown epitaxially by UHVCVD to form NMOSFET and relaxed Si cap layer with strained SiGe layer to form PMOSFET as comparison to bulk sample. From which we can draw a conclusion that the hole mobility can experience a 15% improvement in the strained SiGe layer while the electron mobility can experience a 48.5% improvement in the strained Si layer.In the second part, we introduce the advantages of SOI devices together with their corresponding mechanisms: free of latch-up effect, low parasitic capacitance, easy to form shallow junctions and so on. Then we studied the BMHMT method of SOI MOSFET and its merit: larger drive current which enables it to be the candidate of BJT in realizing BICMOS circuits. Besides exploration and understanding in theory, we also discussed about many design problems, including device design, 版图design and process parameter design problems. Moreover, we throw some supposes on those abnormal phenomenon and try to verify them by simulation.We simulated and adjusted the energy and dose of implant impurity by the aid of Silvaco software so as to confine the Vt value in a reasonable range and finally we got eligible device samples. According to the structure we designed, the SiGe material grown by UHV/CVD was analyzed by DCXRD, TEM, SIMS and AFM.更多还原