【摘要】 为减小脉冲关断延迟，提出了一种用于数字峰值电流模Buck的高精度数字脉冲宽度调制器(DPWM)的设计方案。采用粗调与细调相结合的分段式架构思想，粗调部分由全局时钟控制计数器-比较器模块构成，细调部分由锁相环组成的相移电路、计数器-比较器、多路选择器和逻辑门构成，以此产生不同精度的两段式延迟叠加，实现较高的DPWM输出精度。采用Vivado和Xilinx7系列FPGA,仿真并测试了搭载高精度DPWM的Buck。仿真结果表明，DPWM时间分辨率为250 ps,精度为0.01%。此外，测试结果表明，与低精度DPWM相比，设计的高精度DPWM一定程度上抑制了系统的极限环振荡，提高了Buck的环路带宽及系统稳定性。更多还原

【Abstract】 To reduce the pulse turn-off delay, a design scheme of high precision digital pulse width modulation(DPWM) for digital peak current mode buck was presented, and a segmented architecture concept was adopted by using a combination of coarse and fine adjustment. The coarse adjustment section consisted of a counter-comparator module controlled by a global clock. The fine adjustment section consisted of a phase-locked loop(PLL) based phase-shifting circuit, counter-comparator, multiplexer and logic gates. This generated a two-stage delay accumulation with different accuracies, achieving higher DPWM output precision. The buck converter equipped with the proposed high precision DPWM was simulated and tested in Vivado and Xilinx 7 series FPGAs. The experimental results show that the time resolution of DPWM is 250 ps, and the accuracy is 0.01%. Furthermore, the test results indicate that compared with the low precision DPWM, the proposed high precision DPWM partially suppresses the system’s limit cycle oscillation, thus improves the loop bandwidth of the buck converter, and enhances the system’s stability.更多还原