【摘要】 基于150 mm 0.35μm CMOS工艺，利用Silvaco TCAD软件，针对50μm厚硅基上NMOS与PMOS器件、多晶硅-介电层-多晶硅（PIP）电容和N⁺型多晶硅电阻，在单轴状态不同弯曲半径下，仿真了压缩与拉伸对器件电学参数变化的影响程度。结果表明，单轴拉伸与压缩弯曲使NMOS的阈值电压最大漂移0.46 mV,使PMOS阈值电压最大漂移0.33 mV。漏极电流随变形量线性变化，NMOS压缩时系数为-0.132 95,NMOS拉伸时系数为0.006 01。PMOS拉伸时系数为-0.104 47,PMOS压缩时系数为-0.110 7。电阻阻值随变形量呈线性变化，当掺杂浓度分别为1×10¹⁹,2×10¹⁹,3×10¹⁹,4×10¹⁹,5×10¹⁹时，系数分别为247,498,766,1 016,1 301。电容最大变化值和初始值不超过0.5%,结论归纳为无失配影响。这些结果与实验吻合，验证了模型的正确性，为研制降低退化的柔性硅基集成电路打下基础。更多还原

【Abstract】 Based on a 150 mm 0.35 μm CMOS process, in the NMOS and PMOS devices, Polysilicon-Insulator-Polysilicon（PIP） capacitors and N⁺ type polysilicon resistors with different bending radii on a 50 μm silicon substrate in a uniaxial state, the influence of tension and compression on the changes in electrical parameters of the devices was simulated by using the Silvaco TCAD software. The results show that the uniaxial tensile and compressive bending can make the threshold voltage of NMOS drift 0.46 mV and PMOS 0.33 mV. The drain current changes linearly with the amount of deformation. The coefficient of NMOS compression is-0.132 95, and the coefficient of NMOS tension is 0.006 01. The coefficient of PMOS tension is-0.104 47, and the coefficient of PMOS compression is-0.110 7. The resistance value changes linearly with the amount of deformation. When the doping concentration is 1×10¹⁹, 2×10¹⁹, 3×10¹⁹, 4×10¹⁹, 5 ×10¹⁹, the coefficient is 247, 498, 766, 1 016, 1 301 respectively. The maximum change of the capacitance value and the initial value do not exceed 0.5%, and the conclusion is that there is no mismatch effect. These results are consistent with experimental changes, demonstrating the correctness of the model and laying the foundation for the development of flexible silicon-based integrated circuits with reduced degradation.更多还原