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铁电负电容晶体管的研究进展

A State-of-the-art Review on Ferroelectric Negative Capacitance Transistor

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【作者】 谭欣翟亚红

【Author】 TAN Xin;ZHAI Yahong;School of Micro-Electronics and Solid-State Electronics,University of Electronic Science and Technology of China;

【通讯作者】 翟亚红;

【机构】 电子科技大学微电子与固体电子学院

【摘要】 铁电负电容晶体管的亚阈值斜率可低于60 mV/dec的理论极限,是未来突破晶体管工作电压VDD和器件尺寸进一步减小瓶颈的关键。自2008年低功耗负电容晶体管的概念被提出以来,该晶体管因简单的器件结构和优异的电路性能而一直受到业界学者的广泛关注。然而,这种基于具有负电容特性铁电材料的晶体管的缺点也日渐凸显,特别是负电容的不稳定性对该晶体管的应用造成严重阻碍。相比传统晶体管,负电容晶体管应用于低功耗电路具有两大优势:(1)亚阈值斜率可低于60 mV/dec,降低电路工作电压的同时开关电流比不会下降,静态泄露电流不增加;(2)器件尺寸更小,减小电路面积。然而,负电容晶体管由于铁电材料的滞回特性,在开关电路中具有严重的滞回现象,导致电路逻辑紊乱,无法正常工作。不仅如此,负电容成因的复杂性也使其建模非常困难。因此,近十年来除研究铁电材料种类和参数对器件性能的影响外,研究者们还整理出了决定滞回现象的关键因素,并提出了有效抑制滞回现象的方法。目前,通过调整铁电负电容和晶体管电容的比例,滞回窗口已经可以减小到近乎为零。而与实验图形较吻合的负电容数学模型直到2017年才出现,但模型中的数据还没有科学的测定方法,目前还处于发展完善阶段,仍需要大量的研究和探索。负电容晶体管制备过程简单,工艺和标准CMOS工艺兼容,基底MOSFET制作完成后,将具有负电容特性的铁电材料沉积在栅上形成叠栅。负电容晶体管制作的难点在于稳固铁电和氧化物界面、减少缺陷空位。目前,国内外已出现流片成功的负电容晶体管,成品测试的最小亚阈值斜率可达16 mV/dec,但滞回现象出现的概率非常大,并且在提高器件的疲劳性和稳定可靠性方面还需要投入更多的研究。使用频率较高的负电容材料有PbZrTiO3(PZT)、SrBi2Ta2O9(SBT)、P(VDF-TrFE)、铪基氧化物等,其中铪基氧化物因环保、体积小、性能优异被认为是可投入实际生产的铁电负电容材料。本文探讨了铁电负电容晶体管的工作原理,分析了负电容特性的物理机理和实验测试方法,给出国际上各研究机构在负电容晶体管(NCFET)方面的研究进展情况,最后分析了未来NCFET在器件结构、材料及可靠性方面的发展问题。

【Abstract】 It is possible for ferroelectric negative capacitance transistor to make the sub-threshold swing lower than the theoretical limit of 60 m V/dec,which is the key to break through the bottleneck of reducing working voltage VDDand device size in the future. Since the concept of low power consumption negative capacitance transistor was proposed in 2008,this kind of transistor has been attracting numerous attention from researchers thanks to its simple device structure and excellent circuit performance. Nevertheless,the weakness of the transistor that based on ferroelectric materials with negative capacitance characteristics are becoming increasingly prominent,particularly,the instability of negative capacitance. It must be a serious block for the application of the transistor. Compared with conventional transistors,negative capacitance transistors exhibit two great advantages when applied to low-power circuits. First,the sub-threshold slope can be lower than 60 m V/dec,and there will be no decline in switching current ratio and no increase in static leakage current while the circuit operating voltage is reduced. Second,the device size can be smaller which contribute to the reduction of circuit area.However,due to the hysteresis characteristic of ferroelectric materials,the negative capacitance transistor show serious hysteresis in switching circuit,leading to the disorder of logic circuit and abnormal working situation. Besides,the complexity of the cause of negative capacitance makes it quite difficult to be modeled. Hence,in recent 10 years,in addition to studying the effects of ferroelectric material and its parameters on device performance,the researchers have also put great efforts in sorting out the key factors that dominate the hysteresis phenomenon,and proposed several effective methods to suppress hysteresis phenomenon. At present,hysteresis window can approach to zero through adjusting the proportion of negative capacitance and transistor capacitance. The mathematical model of negative capacitance,which was in good agreement with the experimental results,did not appear until 2017. Whereas,there is no scientific measuring method for the parameters in the model,and further researches and explorations are still needed.The fabrication process of negative capacitance transistor is simple,and compatible with standard CMOS process. After the completion of baseline MOSFET,ferroelectric material with negative capacitance characteristics are deposited on the top of the gate to form a cascade gate. The difficulty of preparing negative capacitor transistors lies in stabilizing the interface between ferroelectric and oxide and reducing the defects and vacancies. Currently,negative capacitance transistors,whose minimum subthreshold slope of the final product can reach as low as 16 m V/dec,have been successful fabricated in laboratory both at home and abroad. However,it suffers from extremely high occurence probability of hysteresis,and more research is needed to improve the fatigue ability,stability and reliability of the devices. Ferroelectric materials that are commonly used in negative capacitance transistor include Pb ZrTiO3( PZT),Sr Bi2 Ta2 O9( SBT),P( VDF-TrFE),hafnium-based oxides. Among them,hafnium-based oxides are recognized as suitable materials for practical production and application because of their environmental friendliness,small size,and excellent performance.In this article,the working principle of ferroelectric negative capacitance transistor is discussed,the physical mechanism and experimental test method of negative capacitance characteristics are analyzed,the latest progress in negative capacitance transistor( NCFET) made by worldwide institutions is introduced. Finally,the future development direction of NCFET in device structure,material selection and device reliability is proposed.

【基金】 电子元器件可靠性物理及其应用技术重点实验室开放基金(ZHD201601);中央高校基本科研业务费专项资金(ZYGX2016J047)~~
  • 【文献出处】 材料导报 ,Materials Reports , 编辑部邮箱 ,2019年03期
  • 【分类号】TN32
  • 【被引频次】6
  • 【下载频次】776
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