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轨到轨电压比较器的设计

Design of the Rail to Rail Voltage Comparator

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【作者】 邱伶俐刘章发

【Author】 Qiu Lingli;Liu Zhangfa;Electronic Information Engineering College,Beijing Jiaotong University;

【机构】 北京交通大学电子信息工程学院

【摘要】 比较器在模数转换及其他模拟功能模块中都是非常重要的器件,其速度和精度直接影响模块的功能。采用SMIC 0.18 CMOS混合信号工艺,设计了一种轨到轨电压比较器,电路结构主要包括前置放大器、锁存器和输出缓冲电路,此外,采用一种β倍增的自偏置基准电路提供偏置电流。结果表明,在3.3 V的供电电压下,提供共模范围为300 m V~3.3 V的信号,可分辨输入信号的最小频率为200 MHz,单级运放相位裕度大于60°,输出信号占空比为40%~60%,比较阈值约为10 m V,输入输出延时小于5 ns,功耗小于18 m W,版图面积小于200μm×150μm。该比较器的失真较小,在整个输入信号范围内有较高的共模抑制比,较大限度地提高了电路的性能。

【Abstract】 The comparator is an important device which is often used in the analog-to-digital conversion and other function module,the speed and accuracy of comparators affect the module performance directly.Using SMIC 0. 18 CMOS mixed signal process,a rail-to-rail voltage comparator was designed. The circuit structure mainly included a pre-amplifier,latch and output buffer circuit. In addition,a β multiplication benchmark circuit was adopted to provide the bias current. The results show that under the power supply voltage of 3. 3 V,the common mode range of the input signal is 300 m V-3. 3 V,the minimum frequency resolution of the input signal can reach 200 MHz,the single stage phase margin of the operational amplifier is more than 60°,the duty ratio of the output signal is 40%-60%,the comparison of the threshold is about 10 m V,the input and output delay is less than 5 ns,the power consumption is less than 18 m W,and the layout area is less than 200 μm × 150 μm. The comparator has a lower distortion and a higher common mode rejection ratio in the whole range of input signal. And the performance of the circuit was improved.

  • 【文献出处】 半导体技术 ,Semiconductor Technology , 编辑部邮箱 ,2015年01期
  • 【分类号】TN722
  • 【被引频次】2
  • 【下载频次】525
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