【摘要】 在详细分析DDS的基础上,针对传统DDS在输出频带范围和输出杂散上的缺陷,提出了一种高速、低功耗的DDS数字电路设计方案。利用相位补偿和相位分路技术,在保持工作频率不变的情况下有效地提高了DDS输出频率,同时采用混合型CORDIC算法实现相幅转换,以优化其在运算速度和相位精度方面的性能。在1.2V,25℃,TT条件下进行仿真,结果表明,当时钟频率为500 MHz时,DDS输出信号SFDR达到88.068dB。更多还原

【Abstract】 A high-speed low-power consumption DDS digital circuit was proposed on the basis of analyzing DDS for avoiding the defects of the output frequency within the band range and output stray in the traditional DDS circuit.The phase compensation and truncation technology were used,the output frequency of the DDS was improved effectively under the condition which the working frequency was constant.Also the transformation of amplitude to phase was realized by the hybrid CORDIC algorithm,so the operation speed and the precision of phase were increased.The simulation results showed that at 1.2V,25 ℃,TT,the measured SFDR is 88.068 dB at 500 MHz clock frequency.更多还原