【摘要】 介绍了一种用于高速流水线ADC双沿采样的时钟占空比稳定电路。在传统占空比稳定电路的基础上,增加含连续时间积分器的反馈环路,并设计了时钟周期检测电路,同时可通过SPI配置积分器的参考电压,在片外调节芯片制造过程中产生的误差,并在前端增设一个高增益带宽时钟放大器,用来放大幅度很小(Vp-p<100mV)的差分输入时钟信号。电路采用0.18μm 1.8V 1P5MCMOS工艺,可对频率范围为50~250MHz、占空比范围为10%~90%的输入时钟进行稳定调节,时钟峰-峰值抖动约为0.3ps@250MHz。更多还原

【Abstract】 A clock duty cycle stabilizer circuit was proposed for double-edge sampling in high-speed pipelined ADC.A feedback loop containing continuous-time integrator was added to conventional duty cycle stabilizer,and a clock-cycle detection circuit was designed.The circuit provided an SPI configurable reference voltage to adjust errors in manufacturing process.A wide gain-bandwidth amplifier was included into the front-end to amplify differential input clock signals with low amplitude(Vp-p<100mV).Implemented in 0.18μm 1.8V1P5MCMOS technology,the proposed circuit could regulate input clocks with duty cycle from 10%to 90% and frequency range between 50MHz and 250MHz,with a peak-to-peak jitter of about 0.3ps at 250MHz.更多还原