【摘要】 针对深亚微米条件下线延迟超越器件的延迟影响芯片性能的问题,提出一种新的片上总线模型和架构.采用多值逻辑传输模式实现片上模块间的通信;采用地址预置技术,提高基于四值逻辑的片上模块间的数据传输效率.ADMS仿真结果表明,相对于二值地址预置总线,在保持相同数据吞吐量时,可以使总线的数量明显减少;在保持相同总线数目时,数据吞吐量提高2倍.更多还原

【Abstract】 As the delay of interconnects might exceed the delay of the devices in very deep submicron realm,a novel on-chip bus structure model is proposed and designed.Multiple-valued logic(MVL) technique was used for communication between modules.Address-presetting was employed to improve the transmission efficiency.The designed structure was evaluated by ADMS simulation in a 0.18 μm CMOS technology.The results show that,corresponding to address-presetting binary bus,the number of bus is reduced significantly.In other words,with the same number of bus,the data throughput of designed bus using four-valued-logic technique could be increased by two times.更多还原