【摘要】 在半导体器件的制造过程中,尤其是在0.18um及其以下的制造工艺中,自对准金属硅化物(Salicide,Self-Aligned Sili-cide)工艺是一项极其关键,同时也涉及到复杂工艺整合的工艺技术。它直接决定了所制造的半导体器件能否达到EDR(Electrical Design Rule)所规定的电学性能,同时还决定了半导体产品中几千万个器件的均一性和可靠性。本文主要通过分析半导体WAT(Wafer Acceptance Test)测试中P型器件饱和电流Idsat不稳定的现象,借助FA(Failure Analysis)手段,提出了造成这一现象的失效模型,最后通过合理的实验设计和分析,从工艺整合的角度,提出了在0.13um逻辑产品制造工艺中,形成均一稳定的低电阻金属钴硅化物(Co-Salicide)的具体解决方法。更多还原

【Abstract】 During the manufacture process of the semiconductor devices, especially for the technologies of 0.18um and below, Salicide (Self-aligned Silicide)formation process is one of the most important processes related with complicated integration problems.Its performance not only determinates whether the devices manufactured by it could meet the electrical requirement of EDR (Electrical Design Rule), but also determinates the uniformity and reliability of the tens of millions devices in the semiconductor products.In this paper, we analyzed the unstable phenomenon of PMOS Idsat during the device WAT (Wafer Acceptance Test)test and proposed the failure model of this phenomenon through FA (Failure Analysis)method.With logical experiment design and result analysis, we come out one detailed solution for the formation of uniform Co-Salicide with low Rs in the manufacture process of 0.13um logic product from the integration point of view.更多还原