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一种图形加速器和着色器的体系结构

Hardware Accelerator and 3D Pixel Shader Architecture for Computer Graphics

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【作者】 韩俊刚蒋林杜慧敏曹小鹏董梁孟李林赵全良殷诚信张军

【Author】 Han Jungang1),Jiang Lin1),Du Huimin1),Cao Xiaopeng1),Dong Liang1),Meng Lilin1),Zhao Quanliang1),Yin Chengxin1),and Zhang Jun2)1)(ASIC Design Center,Xi’an University of Posts and Telecom,Xi’an 710071)2)(Department of Electronic Engineering,Airforce Engineering Academy,Xi’an 710038)

【机构】 西安邮电学院专用集成电路设计中心空军工程大学电子工程系

【摘要】 为了适应智能手机和网本机对于图形加速器的需求,提出一种二维图形加速器和三维像素着色器的体系结构.该体系结构包括自主设计的VLIW指令集和可重组的数据驱动流水线.针对通常将图像帧划分成多个块,且每块由一个微引擎处理的方法可能造成微引擎的负载不均衡的问题,采用按扫描行分配的并行存储和处理结构,其中每个扫描行的处理任务按照需要动态地分配给微引擎.为了评估和实现该体系结构,建立了性能仿真平台、系统仿真平台和RTL仿真平台,并用C++语言编写性能仿真平台评估了该体系结构对性能的影响.模拟实验结果表明,新颖的存储/任务映射方法可以充分地利用处理器资源,降低存储访问的冲突,有利于改善并行处理的可扩展性.文中还讨论了自主设计的图形产生器、图像变换器和VLIW微引擎的结构以及相关的图形硬件加速算法.

【Abstract】 To meet the increasing demand for graphics accelerator in smart hand phone and network notebook,a preliminary architecture for 2D graphics accelerator and 3D pixel shader is presented.The architecture includes a VLIW instruction set,a reconfigurable data driven pipeline and micro-engines.Instead of using traditional parallel processing and task partition scheme,a new memory task mapping method is proposed,which may dynamically assign the task for each scan-line to the micro-engines.In order to assess the efficiency of the architecture,the performance simulation platform,system simulation platform and RTL simulation platform are built.The simulation results show that the new method can be used to improve the utilization of computational resources and reduce frame buffer memory access conflict.In addition,the paper also discusses the structure of graphics generation unit,image transformation unit,the VLIW micro-engine shader,and the relevant graphics acceleration algorithms.

  • 【文献出处】 计算机辅助设计与图形学学报 ,Journal of Computer-Aided Design & Computer Graphics , 编辑部邮箱 ,2010年03期
  • 【分类号】TP391.41
  • 【被引频次】50
  • 【下载频次】393
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