Security strategy of powered-off SRAM for resisting physical attack to data remanence

【摘要】 This paper presents a security strategy for resisting a physical attack utilizing data remanence in poweredoff static random access memory(SRAM).Based on the mechanism of physical attack to data remanence,the strategy intends to erase data remanence in memory cells once the power supply is removed,which disturbs attackers trying to steal the right information.Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation.Implemented in 0.25μm Huahong-NEC CMOS technology,an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2μs and data remanence is successfully eliminated.Compared with conventional SRAM,the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.更多还原

【Abstract】 This paper presents a security strategy for resisting a physical attack utilizing data remanence in poweredoff static random access memory(SRAM).Based on the mechanism of physical attack to data remanence,the strategy intends to erase data remanence in memory cells once the power supply is removed,which disturbs attackers trying to steal the right information.Novel on-chip secure circuits including secure power supply and erase transistor are integrated into conventional SRAM to realize erase operation.Implemented in 0.25μm Huahong-NEC CMOS technology,an SRAM exploiting the proposed security strategy shows the erase operation is accomplished within 0.2μs and data remanence is successfully eliminated.Compared with conventional SRAM,the retentive time of data remanence is reduced by 82% while the operation power consumption only increases by 7%.更多还原