节点文献
RS 485接口芯片中的迟滞比较器设计
A Novel Comparator with Hysteresis for RS 485 Interface Chip
【摘要】 基于RS 485通信协议设计接收电路中的比较电路。比较电路采用带有源电流镜的折叠式共源共栅运放,单端输出,在折叠点处增加4个NMOS管为电路提供正反馈,并通过适当的调节其中2个的宽长比来改变迟滞电压的范围。采用CSMC 0.6μm COMS工艺的HSpice仿真结果表明,此电路能够产生大约±200 mV的迟滞电压,并且当数据传输速率达到2.5 Mb/s时也能正常工作,比通常的比较器更能满足RS 485协议的要求。
【Abstract】 A novel comparator with hysteresis for RS 485 communication is presented,based on folded cascode Op Amp with active current mirror,single-ended output,adding four NMOS at folded point to supply positive feedback.The range of hysteresis voltage is changed by changing W/L of two of them properly.HSpice simulation with CSMC 0.6 μm COMS technology shows that,it can bring hysteresis voltage about ±200 mV,and as data rate reaches up to 2.5 Mb/s,it also works correctly.It can satisfy the RS 485 communication more than other 485 comparators.
【Key words】 RS 485; folded cascode Op Amp; hysteresis voltage; positive feedback;
- 【文献出处】 现代电子技术 ,Modern Electronics Technique , 编辑部邮箱 ,2008年02期
- 【分类号】TP274.2
- 【被引频次】8
- 【下载频次】345