【摘要】 考虑到温度和工艺参数浮动的影响,对休眠双阈值footed多米诺电路的漏电流特性进行了系统的量化研究和比较,得到了不同温度下的最佳休眠状态.基于65和45nmBSIM4模型的HSPICE仿真表明:与业已提出的CHIL(时钟为高,输入均为低电平)状态和CHIH(时钟和输入均为高电平)状态相比,本文提出的CLIL(时钟和输入均为低电平)状态更有利于减小低温下电路的漏电流和高温下的多扇入电路的漏电流.而且,分析了工艺参数的浮动对双阈值footed多米诺电路的漏电流特性的影响,并给出了温度和工艺参数浮动下,双阈值footed多米诺电路漏电流最小的休眠状态.更多还原

【Abstract】 Considering the effect of temperature and process variations,the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage(Vt)footed domino circuits.HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state(the clock signal and inputs are all low)is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature,as compared to the conventional CHIL state(the clock signal is high and inputs are all low)and the CHIH state(the clock signal and inputs are all high).Further,the influence of the process variations on the leakage current characteristics of the dual Vt footed domino circuits is evaluated.At last,temperature and process variation aware new low leakage current setup guidelines are provided.更多还原