【摘要】 用简单的鉴频鉴相器结构实现了一个快锁定低抖动的锁相环.鉴频鉴相器仅仅由两个异或门组成,它可以同时获得低抖动和快锁定的性能.锁相环中的电压控制振荡器由四级环形振荡器来实现,每级单元电路工作在相同的频率,并提供45°的相移.芯片用0.18μmCMOS工艺来实现.PLL输出的中心频率为5GHz,在偏离中心频率500kHz处,测量的相位噪声为-102.6dBc/Hz.锁相环的捕获范围为280MHz,RMS抖动为2.06ps.电源电压为1.8V时,功耗仅为21.6mW(不包括输出缓冲).更多还原

【Abstract】 A fast-locking,low-jitter,phase-locked loop (PLL) with a simple phase-frequency detector is proposed.The phase-frequency detector is composed of only two XOR gates.It simultaneously achieves low jitter and short locking time.The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45°.The PLL is fabricated in 0.18μm CMOS technology.The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is -102.6dBc/Hz.The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps.The power dissipation excluding the output buffers is only 21.6mW at a 1.8V supply.更多还原