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A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs

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【作者】 宁宁； 吴霜毅； 王向展； 杨谟华；

【Author】 NING Ning,WU Shuang-yi,WANG Xiang-zhan,YANG Mo-hua State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China Chengdu 610054 China

【机构】 State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China； State Key Laboratory of Electronic Thin Films and Integrated Devices University of Electronic Science and Technology of China； Chengdu 610054 China；

【摘要】 The effects of stage numbers on power dissipation of pipeline analog-to-digital converter(ADC) are studied and a novel design method aiming for power optimization is presented. In this method,a minimum comparator number algorithm(MCNA) is first introduced,and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution,an optimization method is established,which examines the precise function between ADC power and stage resolutions with a parameter of power ratio(Rp). For 10-bit pipeline ADC with scaling down technology,the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.

【Abstract】 The effects of stage numbers on power dissipation of pipeline analog-to-digital converter(ADC) are studied and a novel design method aiming for power optimization is presented. In this method,a minimum comparator number algorithm(MCNA) is first introduced,and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution,an optimization method is established,which examines the precise function between ADC power and stage resolutions with a parameter of power ratio(Rp). For 10-bit pipeline ADC with scaling down technology,the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.

【关键词】 minimum comparator number algorithm； pipeline analog-to-digital converter； power dissipation； scaling down； stage resolution；
【Key words】 minimum comparator number algorithm； pipeline analog-to-digital converter； power dissipation； scaling down； stage resolution；
【基金】 Supported by the National Natural Science Foundation of China (No. 60072004)
  • 【文献出处】 Journal of Electronic Science and Technology of China ,中国电子科技(英文版) , 编辑部邮箱 ,2007年01期
  • 【分类号】TN792
  • 【被引频次】2
  • 【下载频次】69
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