【摘要】 设计了一个用于10位100 MHz采样频率的流水线A/D转换器的采样保持电路。选取了电容翻转结构;设计了全差分套筒式增益自举放大器,可以在不到5 ns内稳定在最终值的0.01%内;改进了栅压自举开关,减少了与输入信号相关的非线性失真,提高了线性度。采用TSMC 0.25μm CMOS工艺,2.5 V电源电压,对电路进行了仿真和性能验证,并给出仿真结果。所设计的采样保持电路满足100 MHz采样频率10位A/D转换器的性能要求。更多还原

【Abstract】 A sample-and-hold(S/H) circuit for 10-bit 100 MS/s pipelined A/D converters is presented.The S/H circuit is based on the capacitor flip-around architecture with gain-boosted telescopic cascode amplifier,which can settle in less than 5 ns at 0.01% of the final value.A modified bootstrapped switch reducing nonlinearity related to input signal was designed.The circuit is simulated and analyzed based on TSMC’s 0.25 μm CMOS process.Simulation results show that the S/H circuit has a good performance that meets the requirement of 10-bit A/D converter with 100 MHz sampling frequency.更多还原