【摘要】 本文提出了一种Verilog RTL(Register Transfer Level)代码域故障模型和相应的测试点生成策略。该故障模型能准确全面地反映导致域错误的原因,而且需要测试点较少。与现有的一些故障模型做了比较,证明这种域模型和策略是有效可行的。更多还原

【Abstract】 A domain fault model of Verilog RTL(Register Transfer Level) code and the corresponding domain-testing strategies are proposed.This model correctly and fully reflects the reasons causing the domain error.Comparison is made between the domain fault model and other fault model.The result shows that the domain fault is accurate and efficient.更多还原