【摘要】 在国内首次将等效氧化层厚度为1·7nm的N/O叠层栅介质技术与W/Ti N金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1·7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/Ti N金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1·5V,VGS=±1·8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84·46mV/dec ,34·76mV/ V和0·26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107·4mV/dec ,54·46mV/ V和0·27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.更多还原

【Abstract】 By complementing the equivalent oxide thickness (EOT) of a 1.7nm nitride/oxynitride (N/O) stack gate dielectric (EOT=1.7nm) with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time.The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric,non-CMP planarization technology,a T-type refractory W/TiN metal stack gate electrode,and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme.Using these optimized key technologies,high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated.Under power supply voltages of V_ DS =±1.5V and V_ GS =±1.8V,drive currents of 679μA/μm for nMOS and -327μA/μm for pMOS are obtained.A subthreshold slope of 84.46mV/dec,DIBL of 34.76mV/V,and V_ th of 0.26V for nMOS,and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V,and V_ th of -0.27V for pMOS are achieved.These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect,effectively reduced gate tunneling leakage,and improved device reliability.更多还原