【摘要】 设计了一个可重用、可升级的基四流水线结构Viterbi译码器。设计中采用了基四流水、前向追踪、同址写回和分块管理技术,并利用处理单元(PE:ProcessElement)互联技术,对译码器的结构进行了抽象和参数化处理,使卷积码生成多项式、PE个数和回溯深度等可根据实际需要重新配置。在TSMC0.18μmCMOS工艺下,成功地实现了带删除的64状态(4,1,6)Viterbi译码器,电路规模仅3万门,译码速率可达12.5Mbps,功耗为15mW;在ST0.13μmCMOS工艺下,也获得了同样的性能,功耗仅为4.7mW。该Viterbi译码器已被应用于DAB接收机芯片中。更多还原

【Abstract】 A high performance reusable Viterbi decoder is designed. Radix-4-pipeline, trace-forward, same-address-write-back and memory-manage techniques are used to improve its performance, area and power. Under PE architecture, the convolution code, the number of PE, the depth of trace-back, etc, can be all adjustable. Based on TSMC’s 0.18 μm CMOS process, a punctured 64-state (4,1,6) Viterbi decoder is successfully simulated and synthesized, which has 30 000 gates, with a throughput of 12.5 Mbps and 15 mW power.With ST’s 0.13 μm CMOS process, the same performance is achieved, with only 4.7 mW power. The Viterbi decoder has been used in our DAB receiver chip.更多还原