【摘要】 在分析全扫描内建自测试(BIST)较高测试功耗的基础上,总结出几种SMOS VLSI的低功耗BIST技术方案,包括减少待测电路(CUT)输入端的翻转次数、简化线性反馈移位寄存器(LFSR) 结构、部分扫描低功耗BIST方法等。分析结果表明,这些方法不但在保证测试覆盖率的条件下,降低了测试平均功耗和峰值功耗,而且综合应用这几种方法将会使系统功耗指标达到最佳。更多还原

【Abstract】 Based on the analysis of more power consumption of full-scan built-in self test(BIST), several low-consumption technologies of BIST for CMOS VLSI are summarized, including reducing the turned times of CUT, simplifying the LFSR structure and selecting a portion of registers for scan cells and so on. The results show that these methods can reduce the consumption of average power and peak power simultaneously on the condition that test coverage is guaranteed, and that the integration of the several methods utilizing the advantage and remedy will make the low-consumption BIST systems optimum.更多还原