【摘要】 本文概述了ASIC系统中跨时钟域配置模块的多种设计方案以及实现方法,并且着重对分析由于跨时钟域带来的异步时钟问题进行了分析,提出了避免“潜在逻辑错误”发生的解决方案。同时研究了设计方案对后端实现中可能出现的影响,避免了不合理的前端设计给后端实现带来的困难。更多还原

【Abstract】 This article brings forward the cross clock domain design and implementation of configuration module in ASIC system. We analyze the asynchronous clock problem caused by the cross clock domain design and give a solution of the problem that avoid the "potential logical error" in the design. The impact to backend design in our solution is also considered to avoid the difficulty of backend implementation.更多还原