【摘要】 介绍了一种基于电荷泵型锁相环的高速多相时钟发生器。采用常跨导偏置技术,使锁相环的频率响应对工艺、电源电压和温度的变化不敏感;在压控振荡器中采用镜像偏置,使该时钟发生器无需外部精确的偏置电压或电流。电路采用UMC0.18μmN阱CMOS工艺实现。仿真结果显示,在SSS、TTT和FFF三种条件下,环路带宽变化仅为12%,相位裕量只变化0.1°。更多还原

【Abstract】 A high-speed multi-phase clock generator based on charge-pump phase-locked loop (PLL) is presented. By utilizing constant-transconductance biasing technique, the frequency response of the phase locked loop is not sensitive to the variation of process, supply voltage and temperature; and by utilizing replica biasing in the voltage-controlled oscillator (VCO), the generator requires no external high-accuracy biasing. The circuit is implemented in UMC 0.18 μm N-well CMOS process. Simulation results demonstrate that, under SSS, TTT and FFF conditions, the variation of the unity-gain bandwidth of the PLL is only 12% and the variation of phase margin is only 0.1 degree.更多还原