【摘要】 在系统芯片SOC(systemonachip)设计中实现IP核测试复用的芯片测试结构一般包含两个部分:1)用于传送测试激励和测试响应的片上测试访问机制TAM;2)实现测试控制的芯片测试控制器。文章分析了基于测试总线的芯片测试结构,详细阐述了SOC设计中测试调度的概念,给出了一种能够灵活实现各种测试调度结果的芯片测试控制器的设计。更多还原

【Abstract】 A chip test architecture implementing IP core test reuse in SOC design generally includes two parts: 1) a test access mechanism (TAM), which transmits test stimulus and response, and 2) a chip test controller, which realizes test control. A chip test architecture based on test bus is analyzed in the paper, and test scheduling in SOC is explained. Finally, the design of the chip test controller is presented, which is capable of carrying out test scheduling.更多还原