【摘要】 介绍了全数字π/4差分四相移相键控的(DQPSK)调制解调电路原理,应用最新提出的1bit解调算法成功实现解调,该算法大大简化了解调部分的数据处理。分析了新的1bit解调算法理论误码率,比传统的8位π/4DQPSK差1.5dB。当信噪比不低于15dB时,该算法误码率可达10-7,仍是一有效解调方法。在Xilinxise5.2开发环境下用VHDL语言实现调制解调,RTL仿真结果有误码存在,分析发现实现过程中将1kHz时钟用做210(1024)进行分频引起了频率误差,对该误差带来的误码进行仿真分析,同时提出改进的方案,即分频设计时让计数器在0～2n-x之间循环计数,通过仿真证明该方案达到了预期的减小误码率的效果。更多还原

【Abstract】 This paper introduces the circuit principle for an fully digital π/4 shift differentially encoded quadrature phase shift keying (DQPSK) modulation & demodulation. We apply the recently proposed 1 bit demodulation arithmetic,and successfully realized demodulation. This arithmetic greatly reduces data disposal for demodulation section. We analyze the BER theory for 1bit π/4 DQPSK demodulation arithmetic,which is 1.5 dB worse than traditional 8 bits π/4 DQPSK. When SNR is not lower than 15 dB,the BER is 10 -7 . It is still an effective method. Under Xilinx ise5.2 environment,VHDL is adopted to realize modulation & demodulation. We found errors of bit in the RTL simulation. We found that the frequency errors are brought by 1 kHz clock as 2 10 (1 024) for frequency division. We carried out a simulation analysis of errors of bit brought by frequency errors,at the same time ,we suggest a method of improvement,that is let arithmometer take count cyclicly between 0 and 2 n-x . The method achieves the effect of decreased BER shown by simulation analysis.更多还原