节点文献
用虚拟制造设计低压功率VDMOS
Designing low-voltage power VDMOS with virtual fabrication
【摘要】 采用虚拟制造方法设计了低压功率VDMOS器件,并对其进行结构参数、物理参数和电性能参数的模拟测试,确定了器件的物理结构。通过对这些参数和电学特性的分析,进一步优化设计,最终获得了满意的设计参数和性能。
【Abstract】 A low-voltage power VDMOS is designed using virtual fabrication. A virtual device issimulated and the structure of device is settled through the optimizing of process parameters. Afarther optimization is obtained through analyzing and optimizing of the electronics character. Theresults are in good agreement of design anticipation.
【关键词】 虚拟制造;
VDMOS;
虚拟器件;
器件模拟;
【Key words】 virtual fabrication; VDMOS; virtual device; device simulation;
【Key words】 virtual fabrication; VDMOS; virtual device; device simulation;
- 【文献出处】 半导体技术 ,Semiconductor Technology , 编辑部邮箱 ,2004年05期
- 【分类号】TN432
- 【被引频次】8
- 【下载频次】177