【摘要】 介绍一种用在系统可编程逻辑器件 (CPL D)设计 FIR滤波器的方案 .该方案采用 L attice公司 isp L SI CPL D芯片 ,并利用窗函数法实现线性 FIR数字滤波器硬件电路的方法 ,从而提高了FIR数字滤波器的实时性 .设计一个十阶低通 FIR数字滤波器 ,并通过软件程序进行仿真验证和硬件实测 .结果表明 ,此电路工作正确可靠 ,实时性好 ,灵活性强 ,能满足设计要求更多还原

【Abstract】 This paper presents a way of designing FIR filter, using CPLD. It realized a hardware circuit of linear digital FIR filter by the chips of lattice ispLSI and the method of window function. Thus the real time performance of FIR digital filter is increased. Simulation verification and hardware measurement are given on a tenth order and lowpass digital FIR filter through software program. The results have shown that the operation of the circuit is able to meet the requirement of design, with high reliability, good real time performance and enough flexibility更多还原