【摘要】 提出了数模混合集成电路衬底耦合噪声的一种建模方案 :将集成电路芯片的衬底划分为多个 Voronoi图 ,计算各区域的 R、C值 ,在将衬底 RC网络映射到原电路网表之后 ,对新网表进行SPICE模拟 ,分析数模混合集成电路中的衬底噪声。用此模型模拟了两个数模混合集成电路的衬底耦合噪声 ,指出了在模拟电路关键器件周围加保护环是减少衬底耦合噪声的一种有效途径更多还原

【Abstract】 A modeling technique for assessing the impact of substrate coupled switching noise in CMOS mixed digital/analog ICs is presented.In this approach,the substrate lumped element RC is obtained from the circuit layout using a geometric construct called Voronoi diagram.And after computing RC and mapping the substrate RC net to original circuits netlist,the new netlist can be simulated using SPICE simulator to analyze the substrate coupled noise in mixed D/A IC’s.It is found that placing protective ring around key devices of analog circuits is an efficient way to reduce the substrate noise.更多还原