【摘要】 论述了一种大规模、高频率 Ａ Ｓ Ｉ Ｃ 的正向设计过程中所遇到的问题，主要包括在综合过程中由于硬件描述语言形式的限制使得加约束比较困难，因而难以满足时序要求；另外，在布局布线过程中由于电路规模大且有许多高扇出信号而引起的较大互连线延迟，给出了解决这些问题的对策。更多还原

【Abstract】 Problems encountered in the course of designing a very large scale and high frequency ASIC are dealt with.It is found that it is not easy to apply constraints during synthesizing,due to the form of hardware description language.Also,for high fan out signals,the interconnection delay is large because of the very large scale of the circuit.Strategies for solving these problems are presented.更多还原