【摘要】 提出了一种考虑了布线延迟的片上系统设计流程， 并运用一个新的、全芯片的、门级静态时序分析工具支持片上系统设计。实例设计表明， 该设计方法能使设计者得到更能反映实际版图的延迟值， 验证结果更完整、准确， 从而大大加快芯片设计的周期更多还原

【Abstract】 This paper presents the design flow for system on chip(SOC).In this process we not only synthesize our design using actual interconnect delay information,but also use a new,full chip,gate level static timing analysis tool to implement large,SOC designs.We can conclude from the experiment that our method enable designers to accurately analyze the entire chip,converge quickly on meeting timing constraints.更多还原