【作者】 刘健；

【导师】 丁瑞雪；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2021， 博士

【摘要】 随着集成电路技术与电子信息技术的高速发展,作为模拟与数字系统的接口器件,模数转换器(ADC)的应用领域不断拓宽,性能要求不断提高,已经成为便携电子设备、生物医疗、无线通信和智能雷达等应用领域的核心器件。近几年,在电子设备高性能、小型化的发展趋势下,续航能力和系统集成度的重要性持续提升,因此集成电路系统对ADC的功耗和面积提出了更高要求。与其他主流ADC架构相比,逐次逼近型模数转换器(SARADC)具有数字化程度高、面积小、结构简单和功耗低等优势,十分契合新兴应用高能效的系统需求,是当前集成电路技术的研究热点。本文针对中高速芯片的市场应用以及低功耗高能效的主流发展趋势,研究高能效百兆赫兹SAR ADC的系统架构和设计方法。SARADC的功耗来源主要包括采样开关、比较器、电容阵列的开关时序和数字控制逻辑单元。随着量化精度和采样速度的提升,开关时序成为了中高速中高精度SARADC功耗的主要来源。为了满足高能效的设计需求,本文从模块层面出发,针对开关时序进行了建模与分析,提出了 SARADC的冗余电容拆分技术,低位电容复用技术和非对称电容阵列等技术,将量化过程拆分为高低位两部分,减小高位量化过程中的参与电容,有效减少了电容面积,大幅降低了开关功耗。为了进一步提高SARADC的转换效率,本文从结构层面出发,研究了旁路窗口型SARADC的设计方法,其特点是当输入信号出现在预定窗口范围内时,可以跳过不必要的量化周期从而降低SARADC的转换功耗,是低功耗高能效SARADC的最新研究方向。本文对基于电容复用技术的旁路窗口型SARADC进行了建模和分析,并以此为基础,提出了一种窗口自适应技术。相比于传统的窗口实现方式,窗口自适应技术无需增加额外的模拟电路便可以实现旁路窗口判别功能;通过输入范围检测和可配置窗口实现了多窗口范围自动调节功能,可以根据输入信号配置最优的窗口范围,从而提高旁路操作的触发概率;除此之外,提出了一种高效的开关时序用于实现选择跳过算法,可以有效减少窗口产生功耗。本文基于TSMC65nm CMOS工艺,设计并实现了一款8位350 MS/s窗口自适应SAR ADC,芯片面积为0.0096 mm2。测得微分非线性(DNL)和积分非线性(INL)的峰峰值分别为-0.52/+0.78 LSB和-0.48/+0.5 LSB。输入频率为171.111 MHz时,ADC有效位数为7.17位,功耗为1.58 mW,优值(FoM)为31.3 fJ/conv.-step。测试结果表明,基于窗口自适应技术的SARADC性能优异,满足当下应用市场高能效的设计需求。随着电子设备小型化和芯片高度集成化的发展趋势,单一性能的ADC很难满足集成系统的多功能和高能效的设计需求。为了降低集成系统的功耗和面积,本文对可重构SAR ADC进行了重点研究,并提出了可重构电容阵列及一步两位一体化技术,克服了传统可重构SARADC资源利用率不高的问题。其特点是可以根据系统需求改变SARADC的转换模式从而实现功耗、量化精度和信号带宽等性能的同步重构,十分契合多模式、多应用场景,可以进一步优化集成系统的功耗和成本。本文采用SMIC 180 nm CMOS工艺,设计并实现了一款基于可重构电容阵列及一步两位一体化技术的8-9位120-60 MS/s可重构SARADC。该可重构SARADC可以实现低功耗一步一位转换模式和中高速一步两位转换模式,满足多功能集成系统高能效的设计需求。测试结果显示,在一步一位转换模式下,该可重构SARADC可以实现60 MS/s的采样速率。测得DNL和INL的峰峰值分别为-0.21/+0.29LSB和-0.46/+0.41 LSB。当输入信号频率为29.7MHz时,测得ADC有效位数为8.69位,总功耗为1.9mW,FoM值为160 fJ/conv.-step。在一步两位转换模式下,该可重构SAR ADC的量化精度降低1位,转换速率提升一倍,采样速率可以达到120 MS/s。此时,测得DNL和INL的峰峰值分别为-0.31/+0.47 LSB和-0.71/+0.65 LSB。输入信号频率为59.6 MHz时,ADC有效位数为7.46位,功耗为3.5 mW,FoM值为77fJ/conv.-step。更多还原

【Abstract】 Analog-to-digital converter(ADC)is the interface device between the analog system and digital system.With the rapid development of integrated circuit technology and electronic information technology,ADC is widely used in more and more fields,and its performance is continuously improved.It has become the core electronic device in portable electronic equipment,biomedicine,wireless communication,and intelligent radar applications.With the development trend of high-performance and miniaturized electronic equipment in recent years,the durability and integration of electronic equipment are critical.The integrated system puts forward higher requirements for ADC’s power consumption and area.Compared with other ADCs,successive approximation register analog-to-digital converter(SAR ADC)has the advantages of high digitalization,small area,simple structure,and low power consumption.It meets the energy efficiency requirements of emerging applications,which is the research hotspot of current integrated circuits.Based on the medium-high speed application market and the mainstream development trend of low power consumption,this dissertation focuses on the system architecture and design method of the energy-efficient SAR ADC with medium-high speed.The power consumption of SAR ADC includes the sample-and-hold switch,comparator,switching scheme,and digital control logic circuit.With improved accuracy and speed,the switching scheme has become the primary source of power consumption of the SAR ADC with medium-high speed and medium-high precision.In order to meet the design requirements of high energy efficiency,the switching scheme is modeled and analyzed from the module level.Three switching schemes of SAR ADC are proposed,which are the redundant capacitor splitting technology,the low-bit capacitor multiplexing technology,and the asymmetric capacitor array.By splitting the quantization process into high and low parts to reduce the participating capacitor in the high-bit quantization process,the capacitance area and the switching power consumption are effectively reduced.In order to further improve the conversion efficiency of SAR ADC,this dissertation studies the design method of bypass window SAR ADC from the structural level.As the input signal is within the window range,bypass window SAR ADC can skip the unnecessary conversion cycles to reduce the power consumption.It is the latest research direction of low-power and energy-efficient ADC.The DAC-reuse bypass window SAR ADC is modeled and analyzed in this dissertation.On this basis,a window-adaptive technology is proposed to realize the bypass window function without adding additional analog circuits.By the input range detection and the configurable window,the automatic adjustment of multiple window ranges is realized to configure the appropriate bypass window for input signals to improve the trigger probability of bypass operation.Besides,an efficient switching scheme is proposed to achieve the selection skip algorithm,which reduces the power consumption of the window.Based on TSMC 65 nm CMOS process,an 8-bit 350 MS/s window-adaptive SAR ADC is designed.The chip area is 0.0096 mm2.The peak DNL and INL is-0.52/+0.78 LSB and0.48/+0.5 LSB,respectively.With the input frequency of 171.111 MHz,the ENOB is 7.17bit,and the power consumption is 1.58 mW resulting in the FoM of 31.3 fJ/conv.-step.The test results show that the proposed window-adaptive SAR ADC has excellent performance and meets the high energy efficiency requirement of the current application market.With the miniaturization of electronic equipment and high system integration,the single performance ADC is challenging to meet the design requirements of multi-functional and energy-efficient integrated systems.Hence,this dissertation focuses on the reconfigurable SAR ADC to reduce power consumption and area of integrated systems.In order to improve resource utilization,a reconfigurable capacitor array and 2bit/cycle integration technology is proposed,which can change the conversion mode of SAR ADC according to system requirements,reconstruct power consumption,quantization accuracy,and signal bandwidth.It is suitable for multi-mode and multi-application scenarios and optimizes the power consumption and cost of the integrated system.Based on SMIC 180 nm CMOS process,an 8-9 bit 120-60 MS/s conversion mode reconfigurable SAR ADC is designed to realize 1bit/cycle and 2-bit/cycle conversion modes,which can meet the design requirements of the high energy efficiency of the multi-functional integrated system.In the 1-bit/cycle conversion mode,the proposed reconfigurable SAR ADC can achieve a sampling rate of 60 MS/s.The peak DNL and INL is-0.21/+0.2 LSB and-0.46/+0.41 LSB,respectively.With the input frequency of 29.7 MHz,the ENOB is 8.69-bit,and the total power consumption is 1.9mW resulting in the FoM of 160fJ/conv.-step.In the 2-bit/cycle conversion mode,the conversion rate is doubled at the expense of 1-bit accuracy,and the sampling rate can reach 120 MS/s.The peak DNL and INL is-0.31/+0.47 LSB and-0.71/+0.65 LSB,respectively.With the input frequency of 59.6 MHz,the ENOB is 7.46-bit,and the power consumption is 3.5 mW resulting in the FoM of 77 fJ/conv.-step.更多还原