65nm NOR MLC快闪存储器的低功耗高压电路设计和快速编程算法研究

【作者】 史维华；

【导师】 洪志良；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2009， 博士

【摘要】 随着集成电路技术进入纳米时代以及多位存储技术的飞速发展,快闪存储器更早地面临了器件尺寸缩小带来的浮栅间耦合、存储电荷数的减少、短沟道效应以及随机电报信号噪声(RTS)的影响,这些影响增加了多位存储技术实现的难度。而消费类电子市场的蓬勃发展要求快闪存储器具有更快的读写性能、更低的功耗以及更多的功能,如何在这个相对复杂的SOC系统上解决上述问题是目前快闪存储器设计面临的挑战。快闪存储器的读写和擦除操作都和其高压系统息息相关,上电启动管理、待机管理和读写、擦除管理是闪存芯片的主要高压管理系统。在论文研究工作期间,本论文就65nm MLCNOR型闪存对上电启动系统、待机功耗的降低以及编程吞吐率的提高进行了研究和改进。这不仅为进一步提高闪存的编程吞吐率、降低功耗打下基础,而且还可以用于其他工艺技术的闪存设计中以提高芯片的性能。首先,本文就HDSIM卡芯片要求,设计了降低峰值电流的上电启动系统。SIM卡设计要求闪存芯片在无退耦电容情况下,具有较小的峰值电流,传统的设计实现中一般峰值电流在无退耦电容条件下,会达到92mA。测试结果表明该设计在实现芯片要求的12种上电启动控制模式的基础上,有效地将峰值电流降低到49.72mA,满足了SIM卡的标准应用要求。其次,本论文设计实现了闪存芯片的自适应待机功耗管理系统。与传统的待机功耗管理相比,推荐的方法在对漏电的电路节点进行刷新时,将自动检测该节点是否已经恢复目标值,并根据测试结果自动关闭电荷泵以及相关的稳压电路,使刷新时长随工艺、电源电压和温度变化而变化,进而降低了芯片的待机功耗。测试结果表明,该待机功耗管理系统较传统待机管理可以节省8%左右的待机功耗。同时,本论文根据沟道热电子(CHE)的温度特性提出了用温度自适应编程算法提高MLCNOR型闪存编程吞吐率的方案。即根据片上的温度来改变纵向电场和I_d提高编程吞吐率。实验测得,室温下编程吞吐率从原来1.1Mbyte/S提高到采用温度自适应算法后1.4Mbyte/S,编程吞吐率有了近30%的提高。该设计目前处于业内较为领先的水平。此外,本文还对关键电路电荷泵的设计进行了研究,讨论了电荷泵的设计方法、主要性能指标、模型以及版图设计优化。更多还原

【Abstract】 With the development of IC from sub-micrometer era to nanometer, and the emerging of the MLC storing technology, flash memory is facing the key challenges of cell size scaling down, such as the floating gate to floating gate coupling, the random telegraph signals (RTS), the decreasing of the number of electrons stored in the floating gate, and the short channel effect, which increase the difficulty for Multi-Level-Storage technology. Meanwhile, the rapid development of applicateion market requires the high-density, high performance, and low power Flash memory with more functionality. How to solve the above mentioned problems on this sophisiticaed SOC are the hot topics in flash memory design.All the flash memory functionalities are highly dependent on the high voltages. The powerup management, the standby management and the read/ program/ erase control schemes are the high voltage management schemes on flash memory system. In this dissertation, how to improve the program throughput, how to reduce the standby power and how to design the powerup management scheme are discussed. The improvements are proposed and implemented based on analysis.Firstly, this dissertation provides a power-up scheme which applied in the first HDSIM card. The experiment result exhibits, this new power-up scheme can work properly under 12 modes, and more importantly, it significantly reduces the peak current from 92mA to 49.72mA, which meets the HDSIM specification now.Secondly, an adaptive standby management scheme is implemented in this dissertation. It will shut off the pump and the regulator once the leaky nodes achieve target voltages. Compared with the traditional implementation, it will shut off the refresh based on the process, voltage and temperature, which will save the power consumption further. Experiment results show that the new scheme will save 8% power consumption when compared with the traditional scheme.Meanwhile, this dissertation presents the implementation of improving MLC NOR flash memory program throughput based on Channel Hot Electron (CHE)temperature characteristic. Temperature self-adaptive programming algorithm is proposed to increase the I_g according to on-die temperature. Experimental results show that the program throughput increases significantly from 1.1MByte/S without temperature self-adaptive programming to 1.4MByte/S with proposed method under room temperature. It presents a 30% improvement.As the key high voltage component in flash memory, the charge pump is analyzed in detail for low power application. The design methodology, the key design specifications, the simulation model and the consideration of layout are all addressed in this dissertation.Although all of above mentioned is based on the 65nm MLC technology, it can also benefit other flash technology. Furthermore, the proposals and improvements in this dissertation can be used for further improving the program throughput and reducing the power consumption in Flash memory design.更多还原