【作者】 雷庭；

【导师】 孙义和；

【作者基本信息】 清华大学 ， 电子科学与技术， 2011， 博士

【摘要】 在处理器电路中，晶体管尺寸不断缩小所带来的越来越严重的工艺偏差和噪声容限下降等问题，使得出现延时故障的可能性越来越大。为避免延时故障引起的错误，一般采用增加处理器执行时钟周期的方法（用最坏情况的设计数据决策时钟周期），这样势必会降低处理器性能的速度指标。当晶体管尺寸缩小到65nm及以下时，增加时钟周期避免延时故障的方法将使速度指标下降得难于满足设计要求。因此，具有能检测和纠正错误的自查错/纠错设计成为众多研究者关注的焦点。本论文根据应用需要和提高处理器吞吐率的目标，研究和探索一种新的处理器自查错/纠错设计技术。论文主要研究成果如下：提出了基于代表路径的RPED错误探测结构和基于流水线停滞的PSEC纠错机制。论文证明了RPED探测错误的正确性和应用的可行性，给出了其设计规则。经ISCAS’89和ITC’99Benchmark电路实验表明，RPED探测错误的准确率大于99.9%，硬件开销小于1%。理论计算和模拟实验表明，PSEC相比现有其他纠错机制可减小30%以上的平均错误恢复时间。提出了计算处理器在给定时钟周期（频率）下的错误率的理论模型——延时故障概率模型。经实验验证，该模型在给定电源电压和温度变化范围的条件下，可决策和界定在一定错误率下处理器工作的时钟周期。提出了一般情况下采用自查错/纠错设计能够提高流水线处理器吞吐率的判定准则，给出了其充分必要条件的数学形式，具有普遍的应用意义。研究实验表明，采用自查错/纠错设计能否提高处理器吞吐率只与电路延时的概率密度函数和平均错误恢复时间有关，而与查错/纠错功能的实现方式无关。论文在以上研究基础上规划了一种流水线处理器自查错/纠错设计方法和流程，在原流水线处理器电路的基础上，得到具有自查错/纠错功能的处理器电路。经过OpenRisc1200处理器设计实例测试，处理器的吞吐率提高了10%；相比现有公开方法，自查错/纠错单元的硬件开销降低了53%、平均错误恢复时间减少了45%以上。更多还原

【Abstract】 Along with technology aggressively scaling, the design of processors facesproblems such as process variation, noise tolerance decreasing. As these problems arebecoming more and more significant, the probability of delay faults in the circuitincreases. In conventional processor design, clock period is expanded to avoid errorscaused by delay faults, which decreases the speed of the processor. In65nm technologyand below, the lost of speed as a result of avoiding delay faults by increasing clockperiod is too high to meet the requirements. Thus, processors with error-detection anderror-correction have become the focus of research at the present. In view of applicationrequirements and aiming at improving throughput of the processor, a new method ofdesigning processors with error-detection and error-correction has been researched andexplored in this dissertation. The main results of this dissertation are presented asfollows:The representative path based error-detection (RPED) and pipeline stallingbased error-correction (PSEC) are proposed in this dissertation. Thecorrectness and practicability of RPED has been proved and the design rulesare introduced. Experiments on ISCAS’89and ITC’99benchmarks show thatRPED detects the errors with accuracy of more than99.9%. The hardware costof RPED is less than1%. The calculation and simulation results show thatPSEC can reduce average error recovery time by more than30%comparedwith other existing error-correction mechanisms.The probabilistic delay fault model is proposed to estimate the error rate undergiven clock periods when the processor works in power supply voltage andtemperature changing environment. It has been verified by the experiments thatusing probabilistic delay fault model, the clock period of the processor isdetermined on the premise that the error rate is controlled at a certain levelonce the range of power supply voltage and temperature is given.The criterion which gives the sufficient and necessary condition of increasingthe throughput by error-detection and error-correction is presented in thisdissertation. The mathematical expression is universal and can be into general application. It is pointed out that the validity of increasing the throughput byerror-detection and error-correction relies on the probability density function ofthe circuit delay and the average error recovery time, and has nothing to dowith the implementation of error-detection and error-correction.Based on the research above, a design method and flow of processors witherror-detection and error-correction has been explored. The circuit of theprocessor with error-detection and error-correction is acquired from theoriginal pipeline processor circuit. Implementation of OpenRisc1200processorshows that the design method in this dissertation can improve the throughputby10%. Compared with other existing methods, the cost of error-detection anderror-correction is reduced by53%and average error recovery time is reducedby more than45%.更多还原