【作者】 王向展；

【导师】 杨谟华；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2010， 博士

【摘要】 第五媒体—数字多媒体广播(Digital Multimedia Broadcast,DMB)由于能够实时提供音视频、文字和图像数据等多媒体内容而成为信息科学领域发展最快的热点之一。DMB接收系统包括天线、接收前端、基带音视频解码器和加密系统,其中接受前端是实现微弱广播信号接收到后端数字处理的关键。同时,低成本需求迫使多媒体接收前端芯片的设计由传统的GaAs工艺转向Si CMOS工艺。但CMOS工艺的发展主要针对数字电路优化,且MOS器件具有跨导低、噪声大的劣势。因此,为实现移动接收系统的射频模拟前端,就有待于其物理基础研究和关键技术的突破。为此,本论文基于国内DTMB和CMMB标准,重点针对多媒体接收前端各单元芯片IP物理设计和集成实现,重点开展集成电感建模、射频LNA与VGA、模数AD/数模DA转换器诸核心模块的理论、架构研究与关键单元电路的设计。一、基于电磁场理论详细分析了集成电感的邻近效应、趋肤效应和衬底涡流损耗等高频寄生效应形成机理与分布特性,通过将部分元等效电路法合理简化,推导出了电感I-V矩阵方程并给出串联电阻Rs(f)和有效电感Ls(f)的求解表达式。对比仿真验证了模型的计算精度与效率,仿真结果说明,低阻Si衬底是影响CMOS RFIC电路设计的严重制约因素。二、在分析现有结构优缺点的基础上设计了LNA和VGA电路并进行优化仿真。其中,LNA在共栅共源结构基础上加入的级间匹配电感使增益提高到18.2dB,而噪声系数降至1.6dB;VGA电路设计中采用有源负载代替电阻并引入密勒效应抑制器件来增大带宽,构造了指数控制近似函数。结果表明,设计的VGA增益控制范围大于60dB,在14dB~78dB范围内随DAC控制电流线性变化,误差小于±1dB,满足射频下增益调整需要。VGA接以DAC输出电流控制,省去电流-电压转换电路,精简面积。三、系统地分析了分段电流舵结构误差源与积分非线性INL的均值、方差等统计学参数,基于随机理论的布朗运动过程对INL指标进行了建模,并以成品率为考查手段对模型进行了验证,给出了电流舵DAC设计时分段比的优化建议。同时,提出了一种利用电阻正负温度系数进行补偿的高精度、高电源抑制比的带隙基准电流源,改善了共栅共源单位电流源的输出阻抗和输出毛刺,通过限幅和提高交叉点设计了一种高速、低毛刺的开关驱动电路,按0.35μm Si CMOS工艺设计规则完成了DAC版图设计。四、结合全并行Flash、流水线Pipeline、逐次逼近SAR A/D转换器结构的优点,提出了新型分段多指针查找比较的模拟/数字转换方案。该方案大大减少了比较器数目,且去掉了普通多步式ADC和流水线ADC结构中必需的MDACs和残差放大模块RAs,从而有效降低了功耗和面积;并分别针对ADC位数是否可均分两种情况,优化了查找算法,导出了最优的级精度选择方法。应用此方案原理设计了3+3+4的分段多分搜索比较算法加流水线的混合模式ADC结构。经二阶系统阶跃响应分析和传输函数推导,提出了一种新型补偿方法,并应用于Folded-Cascode放大器的设计,使运放的建立时间由5.08ns缩短到3.89ns,减少了23.4%。五、基于高速高精度数模混合IC版图设计原理,综合考虑数字部分对模拟部分的干扰、工艺误差分布、差分信号对称性并结合实际工艺情况,应用地线屏蔽、数字/模拟电源分离及对称匹配等布局布线技术,按照0.35μm 2P5M Si CMOS工艺设计规则,完成了ADC整体版图的设计,版图实际尺寸1534μm×2172μm。进而用Calibre PEX提取寄生的电阻、电容元件与器件参数,然后使用HSpice仿真器对整个系统进行后仿真。结果显示,ADC的DNL小于±0.5LSB,INL小于±1LSB,无杂散动态范围SFDR为72.4dB,说明ADC精度达到了10位要求,总功耗215mW,为下一步投片的成功提供了保障。展望未来,围绕移动多媒体接收所涉及的系统架构、射频器件模型、低功耗数据转换和接收前端单片化诸技术领域,仍有待于进一步持续深入地研究。更多还原

【Abstract】 The fifth media—Digital Multimedia Broadcast(DMB) has already become one of the fastest developing hot point in the field of information science for its capability of providing various kinds of multimedia information such as audio, video, text and image. DMB system consists of antenna, receiver, baseband audio/vedio decoder and encrypting system. Among them, receiver is the key hardware to realize receiving of feeble broadcasting signals for post digiatal process. Meanwile, low coast requirement make the designers of receiver IC using Si CMOS process instead of GaAs. But the development of CMOS process primarily aims at the optimization of digital circuits, resulting in low transconductance and large noise for MOS device. Therefore, in order to realize RF analog front end of the receiver system, it need to break through the physical bases and key techneques.In this dissertation, modeling of integrated inductor, theory and structure study on key blocks such as RF LNA and VGA, ADC/DAC, design of critical unit circuits, are performed to realize the physical IP design and integration of mobile receiver system that meets the China standard of DTMB and CMMB.1. Based on the theory of electromagnetic field, this dissertation makes a detailed analysis on the causes and distribution characteristics of the high frequency parasitic effects of integrated inductor, such as proximity effect, skin effect and eddy current losses in the substrate. Through simplifying partial equivalent element circuit methodology properly, I-V equation of inductor is derived and the expressions for series resistance Rs(f) and effective inductance Ls(f) are presented. The calculation accuracy and efficiency of the model presented in this dissertation is verified in comparing simulation. Simulation results also show that Si substrate with low resistivity is a severe restriction for the design of CMOS RFIC.2. Based on the analysis of existing structures, final LNA and VGA circuits are designed and optimized. Among the two critical units, inter-stage inductor is added to cascode LNA structure, resulting a gain increased to 18.2dB, and the noise factor decreased to 1.6dB; resistors are replaced by active loads and Miller Effect restraint transistor is also introduced to increase bandwidth in VGA, additionally, exponentially controlled approximation function is constructed. Gain control range of the designed VGA is greater than 60dB, and the gain changes linearly with the control current of DAC in the range of 14dB~78dB with error less than±1dB. Such performances of the VGA satisfy the need of gain adjustment under radio frequency. Current-voltage conversion circuit is omitted because the VGA is directly controlled by the output current of DAC, thus reducing the area.3. Error sources and statistical parameters such as the mean value, variance of INL of a segmented current-steering DAC are analyzed systematically. The index INL is modeled based on random theory and the process of Brown Motion. The model is verified in terms of yield, and optimization suggestions on segment ratio in current steering DAC are also presented.Meanwile, this dissertation presents a high precision high PSSRR bandgap current reference compensated by the plus and minus temperature coefficients of resistors with feedback to restrain the ripple on power supply, a modified cascode unit current source to obtain high output resistense and low glitch, and a rapid low glitch switch driver with the function of clamping and higher cross points. Finished final DAC layout according to the design rule of 0.35μm Si CMOS process.4. Combining the advantages of Flash, Pipeline and SAR structures. This dissertation presents a novel segmented multi-division search algorithm A/D conversion scheme. Due to the novel A/D conversion scheme, not only the number of comparators is dramatically reduced, MDACs and residual amplification module RAs which are essential in traditional multi-step ADC and Pipeline ADC are also omitted, thus reducing the power consumption and area efficiently. This dissertation also presents the optimized search algorithm, demonstrating the optimized selection method for stage accuracy according to whether the resolution of the ADC can be partitioned equally. Based on the principle of this scheme, a 3+3+4 mixed mode ADC structure combined segmented multi-division search algorithm with pipeline is designed.Through the analysis of step response of two order system and derivation of transfer function, a novel compensation method is presented. Application of the method on the design of a folded cascaded amplifier show that the settling time of the opamp is reduced from 5.08ns to 3.89ns, or 23.4%. Simulation result verifies the efficiency of this method.5. Completed layout of the ADC is finished according to the design rule of 0.35μm Si CMOS process. Based on the design principles of high speed high precision mixed signal IC layout, some important factors such as interference of digital circuits to analog circuits, error distribution of the process, symmetry of differential signals and some practical situations of the process are comprehensively considered. Additionally, placement and routing skills such as ground line shielding and symmetrical matching are applied. Final size of the layout is 1534μm×2172μm. After extracting the parasitic resistor, capacitor and device parameters with Calibre PEX, HSpice simulator is used to post simulate the circuit. Post simulation results show that DNL of the ADC is smaller than±0.5LSB, INL is smaller than±1LSB, SFDR is 72.4dB, and the total power consumption is 215mW, indicating that the accuracy of the ADC achieves 10bit resolution. Thus the success of tape out is guaranteed.Look forward to the future, it should be noted that contimuous deeper researches and developments are still expected on system architechture, RF device model, low-power data converter and monolithic involved in mobile digital multimedia broadcoasting receiver.更多还原