【作者】 王龙海；

【导师】 于军；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2006， 博士

【摘要】 近年来,将铁电材料与半导体器件相结合的新器件逐渐得到广泛的应用。其中新型非挥发铁电存储器(FeRAM)与传统的EEPROM和FLASH非挥发存储器相比,具有操作电压低、功耗低、信息保持时间长、写操作速度快、抗辐射等优异的特性,非常适合嵌入式应用的要求。而铁电电容是FeRAM器件的关键组成部分,所以本论文对用于嵌入式铁电存储器的集成铁电电容进行了研究。铁电薄膜是铁电存储器的基础,根据嵌入式铁电存储器对铁电材料的要求,选择了Zr/Ti比为30/70的PZT为嵌入式铁电存储器用材料。用Sol-Gel法在Pt/Ti/SiO2/Si(100)结构电极上制备出了PbZr0.30Ti0.70O3、PbZr0.30Ti0.70O3/PbTiO3和PbTiO3/PbZr0.30Ti0.70O3/PbTiO3等不同结构的铁电薄膜。对Sol-Gel工艺中溶胶配制、薄膜厚度及均匀性控制、热处理工艺等三个重要的环节进行了优化。通过对不同结构铁电薄膜的微结构与电学性能讨论,指出表面PT层与底部PT层一样也同样可增强薄膜的结晶性能和电学性能,PT/PZT/PT这种夹心结构是一种优化的、适合嵌入式铁电存储器用的铁电薄膜结构。研究了PT层中过量Pb配比对PT/PZT/PT薄膜的微结构与电学性能的影响,发现PT层中过量Pb配比对薄膜的结晶行为的影响很大。PT层中Pb含量是通过影响PT层的结晶,并作为种子层来影响整个薄膜的结晶行为,从而进一步影响薄膜的电学性能。用SFM的PFM和EFM模式对PT/PZT/PT铁电薄膜的电畴结构及其极化保持特性进行研究。在PFM模式下,压电响应的IPP、OPP以及振幅和相位图像中的复杂畴衬度可归因于晶粒的结晶取向和畴排列所致。薄膜的自发极化电畴主要由极化矢量垂直膜平面方向和偏离膜平面垂直方向的c畴所构成。薄膜中的畴壁与C轴取向的薄膜中方向相反的c畴或a畴都可构成180o的畴壁,而90o畴壁由a畴与c畴或180oa畴与90oa畴构成不同。[111]取向的铁电薄膜,90o畴壁由垂直膜平面方向上相同、面内方向相反,或由垂直膜平面方向上相反、面内方向相同的偏离垂直于膜平面方向上的c畴构成;而180o的畴壁则为垂直膜平面方向和面内方向都相反的偏离垂直于膜平面方向上的c畴构成。在EFM模式下,因电场的连续性和表面吸附电荷的影响,表面电势图的衬度区分度较小,不能观察到自发极化的电畴结构,但对外电场的极化有较高的区分度。用EFM模式研究了电畴极化保持特性,其表面电势差随时间的变化遵从指数函数变化规律。采用常规的集成电路工艺制备出了较好的集成铁电电容。分析了集成工艺中铁电薄膜刻蚀损伤的机理,指出采用重新热处理的措施,不能完全恢复刻蚀损伤的原因。根据Sol-Gel薄膜工艺的特点,将铁电薄膜制备工艺与刻蚀工艺相结合,提出了一种新的铁电电容集成工艺方案。避免了常规集成铁电电容工艺中铁电薄膜刻蚀损伤的因素,得到了几乎无损伤的、有良好电学特性的Pt/PT/PZT/PT/Pt集成铁电电容,可满足嵌入式铁电存储器中对集成铁电电容的性能要求,且集成工艺与标准的CMOS完全兼容。根据铁电体的结构特征,将铁电体的晶体原胞等效为一个偶极子。根据偶极子在电场下的运动规律和统计物理学原理,建立了铁电电容的物理模型,得到了极化强度与电场之间的关系表达式。采用不同的实验结果对所建的模型进行了验证,并将所建的模型与通用仿真平台软件Hspice相结合。利用所建的铁电电容模型构建了铁电存储器存储单元的优化设计仿真电路,完成了所有电路的功能仿真。通过分析位线分布电容对存储单元数据读出的影响,用所建的铁电电容模型分析了位线电容优值、灵敏放大器灵敏度对应位线电容的最大值和最小值与铁电电容尺寸的关系,从而优化了铁电电容与位线的版图尺寸。最终设计出了基于0.6μm标准CMOS工艺的128×8bit嵌入式铁电存储器的电路和版图,通过了设计规则的检查,为嵌入式铁电存储器的工艺实现打下基础。更多还原

【Abstract】 Recently, the new devices of semiconductor with ferroelectrics materials are applied in many fields. Ferroelectric nonvolatile random access memories (FeRAM) which utilizes the spontaneous, reorientable polarization of ferroelectric capacitors as a memory state appear to hold good promise for System-on-Chip(SOC) use because their operational voltage is low, write endurance is high, write speed is fast and anti-radialization. Each has an improvement over SOC EEPROMs and FLASH memories. Integrated ferroelectric capacitors are the key part of FeRAM devices, so the integrated ferroelectric capacitors were investigated in this thesis for embedded FeRAM.In FeRAM, information is stored by the polarization direction in a ferroelectric film and the stored datum is read out using the polarization reversal current. Thus, special characteristics are desired for a ferroelectric thin film. According those demands, the PZT ferroelectric materials with Zr/Ti ratio of 30/70 were selected. The different structure multilayer PbZr0.30Ti0.70O3, PbZr0.30Ti0.70O3/PbTiO3 and PbTiO3/PbZr0.30Ti0.70O3/PbTiO3 ferroelectric thin films were deposited on Pt/Ti/SiO2/Si(100)substrate by Sol-Gel method. The technologic parameters such as preparation of precursor solution, control of thickness and homogeneity, heat-treatment were optimized. The microstructure and electric properties of these thin films are investigated. The results indicate that the multilayer PT/PZT/PT thin film has a better electric property. The double-sided PT seed layers enhance not only the microstructure but also the electric properties. It is evident that the PT/PZT/PT multilayer thin film is a promising candidate for FeRAM application. The Pb content in PT layers effects the crystallization of the formation of perovskite-phase of PZT films through the effect of perovskite-phase formation of the PT layers, and further effect the electric property of the films.The domain is the fundament of ferroelectric physics, the domain and domain wall structures were investigated by scanning force microscopy in PFM mode. The out-of-plane polarization (OPP), in-plane polarization (IPP), the OPP amplitude and OPP phase images were obtained. The domain of the film has a complex structure with c-domain and deviated-c-domain which direction deviated from the vertical direction of surface of the film. The complex domain structure is related to the orientation of the crystal grains in the film. For the [111] oriented films, the 180o domain wall is form when deviated-c-domain has the reverse direction in OPP and IPP. The 90o domain wall is form when the domain has the same direction in OPP and reverse direction in IPP, or when it has the reverse direction in OPP and same direction in IPP. In EFM mode, the surface potential images of EFM-response can not reflect the spontaneous polarization of domain due to the continuing of electric field and charge trap in the surface, but can reflect the domain polarization by external electric field. The polarization retention is investigated and shows a stretched exponential time dependence decay law.The MFM structure integrated ferroelectric capacitor with better properties was integrated by a conventional process. The mechanism of damage of ferroelectric thin film in RIE process was analyzed, and the reason why the properties of ferroelectric thin film can not recovery completely by re-annealing was point out. Based on the characteristics of Sol-Gel process, combined the integrated and ferroelectric thin film deposited process, an innovated integrated ferroelectric capacitor process was adopted. The damage factor in conventional process was avoided, and the non-damage integrated ferroelectric capacitor with perfect properties of Pt/PT/PZT/PT/Pt was integrated by the new process. The new integrated process is compatible with standard CMOS process, and the integrated Pt/PT/PZT/PT/Pt ferroelectric capacitor can be used in FeRAM for its perfect properties.Based on the characteristic of ferroelectric microstructure, a cell of ferroelectric crystal is just as an equivalent dipole, so the hysteresis loop characteristic of ferroelecticity is the polarization characteristic of dipole in the electric field. A compact model for description of the P-E hysteresis behavior based on the dipole switching theory and the statistic principle was derived. Simulation results show good agreement with the experiment data for various hystersis loops, and the mathematical description is very simple to be easily inserted into Hspice software for circuit simulation. The design and read/write operation of the FeRAM circuit are carried out under the model. Through simulation, the optimization of the storage capacitance and bit line load capacitance is proposed. Based on the standard 0.6μm CMOS technical process, the circuit, lithographic masks and layout of 128×8bit FeRAM were designed for SoC.更多还原