【作者】 杜振军；

【导师】 马光胜；

【作者基本信息】 哈尔滨工程大学 ， 计算机应用技术， 2003， 博士

【摘要】 芯片设计的日趋复杂化和高速化对设计自动化的理论和方法提出了新的要求。布尔过程论是适应这种要求而提出的新的理论，本文以布尔过程论为理论基础，对该理论进行了拓展，探讨了该理论在复杂高速芯片设计自动化中的应用，在芯片定时、测试生成、验证和综合基础研究方面提出了几个基于该理论的自动化设计的新方法和新算法。 论文首先拓展了布尔过程的理论，提出了以下新的概念、定理、理论模型和数据结构。波形多项式偏导和高阶偏导的新概念，用来精确描述输出跳变与输入跳变之间的关系，并在本文中用来重新定义了电路的敏化和冒险；波形多项式向量的概念，用于形式化描述实际中的多输入多输出的电路，特别是用于统一描述电路模块的功能及定时行为；时序电路的敏化定理，用于时序电路精确定时分析；波形多项式描述跳变及跳变数的定理，用于噪声、功耗等问题的描述；时序电路的完整波形多项式描述，用于时序电路功能和定时行为的统一描述；波形多项式的多项式符号表示和运算的模型以及数据结构，用来实现对波形多项式比较有效的描述和运算。 然后论文进行了布尔过程论在芯片自动化设计中应用的研究。在组合逻辑电路精确定时方面，本文用波形多项式偏导定义的敏化概念改进了解析延时模型，在此基础上建立了基于敏化的延时矩阵以描述电路模块的延时，随后将层次化延时分析方法引入基于延时矩阵的延时分析中，形成一种新的精确的通用电路层次化延时分析方法。实验证明该方法既能大大降低复杂问题的计算时间，又能很好地维持延时的准确性。它还特别适合于片上系统的基于IP的设计方法。 在时序逻辑电路精确定时方面，从时序电路的敏化定理出发，使用本文给出的条件可敏化概念，通过对通路敏化性质的判断建立了一种新的单周期敏化的时序电路最小时钟周期精确确定方法。同传统方法相比，本方法计算出的最小周期既能保证电路的正确计算，又不至于保守，而且能同时计算出组合逻辑部分的延迟；然后从时序电路的波形多项式出发，进一步给出了多周期敏化的最小时钟周期确定方法，适用于有苛刻定时要求的环境。 为了适应超深亚微米电路测试的要求，本文建立了一种新的基于布尔过哈尔滨工程大学博士学位论文程论的逻辑级噪声预测模型，用波形多项式描述的同时发生的跳变数来预测l卜足声大小，并生成能产生最大跳变数目的输入波形;然后同基于波形敏化的长敏化通路选择法相结合，形成一种能产生最大噪声效应的敏化测试波形生成新方法。实验表明，本文的方法可以应用在复杂超深亚微米电路的延时故障测试中，有一定推广价值。 在芯片的综合和验证中，部件的匹配和功能验证是一个基本环节，能以较低的复杂度建立不同设计层次中统一的正则描述形式是一个关键的问题。木文将位级电路波形多项式描述转化成字级多项式描述，提供了一种正则、在多项式时间内可构造的、能够将位级描述转化成字级描述的模型，月_允许简单的合成。该方法可以用来有效判断不同设计层次的描述是否等价，从而可以实现跨设计层次的模块重用、综合和验证。 另外，:基于C语言本人设计开发了一个实验软件系统，该系统包括波形多J一贞式表示模块、敏化通路判定模块、延时计算模块、单周期敏化的最小时钟周期精确确定模块、多周期敏化的最小时钟周期确定方法模块、考虑噪声的测试生成模块和位级波形多项式描述转化成字级多项式描述模块，分别用于对本文各章中提出的自动化设计的模型和方法进行实验验证。更多还原

【Abstract】 The design of complex and high-speed chips requires novel theories and approaches in design automation. Boolean Process theory is recently proposed to meet this requirement. Based on Boolean Process, some theoretical extensions are made and novel techniques in design automation such as timing, test generation and basic research on verification and synthesis are proposed in this paper.Some theoretical extensions are first made in this paper, with the following concepts, theorems and models presented-Partial derivative and high-order partial derivative of waveform polynomial for describing the relation between input transitions and output transitions and redefining circuit sensitization; The concept of waveform polynomial vector for describing a circuit with multiple inputs and outputs, especially for the unified description of circuit modules; A sensitization theorem for sequential circuits for the purpose of exact timing; Theorems for transition numbers in circuits used to solve problems on noise, power consumption and etc; waveform polynomial description for sequential circuits used to give a unified form for the function and timing behavior of a sequtial circuit; And a data structure of generalized list for the representation and manipulation of waveform polynomial.Then studis on new models and new approaches based on Boolean Process in delay automation are made. Analytical delay model is improved with the new concept of sensitization, based on which delay matrix is proposed to describe the delay of circuit modules. Then introducing hierarchical delay analysis methods into delay matrix analysis, a novel exact hierarchical delay ananlysis method is presented. This approach can greatly reduce the computation time on complex problems with good exactness, especially suitable for IP based design.Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single-period sensitization is proposed. Compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high-speed circuit design. Anda retiming scheme based on the above method is also presented to optimize the timing behavior of sequential circuits. Also from waveform polynomials of sequential circuits, a precise clocking method based on multiple-period sensitization is presented.A novel noise estimation method based on Boolean Process is first presented in this paper, using transition numbers to describe noise effects. Then combined with the selection method of long sensitization paths based on waveform sensitization, a test generation approach that could generate the noisiest sensitization waveforms for long sensitizatizable paths is presented. Experimental results in this paper show our approaches can be efficiently used in delay testing for complex circuits with noise effects.In chip synthesis and verification, component maching and verificaion are basic links. It is a crucial issue to establish a unified canonical description form for different design levels with low complexity. A new method that transforms bit-level waveform polynomial to word-level polynomial model is given, allowing for simple composition. This method offers an efficient way to determine whether two descriptions from different design levels are equivalent, so component reuse, synthesis and verification across design levels can be realized.In addition, an experimental system using C language is established, including modules such as representation of waveform polynomial, decision of path senstization, delay computing, clocking based on single-period sensitization, clocking based on multi-period sensitization, test generation considering noise and transformation from bit-level waveform polynomial to word-level polynomial model. They respectively used to test models and techniques proposed in this paper.更多还原