【摘要】 基于高性能FPGA实现的DDS电路是某些对于控制方式、置频速率等方面有特殊要求场合的最佳选择。通过把DDS的核心部件——相位累加器改进为回旋相位累加器,使得存储波形数据的ROM空间降低50%,频率分辨率提升了1倍。另外,在QuartusⅡ,VC与Labwindows/CVI的混合仿真环境下,使得设计完全避免了硬件平台的限制,增加了硬件实现的成功率。更多还原

【Abstract】 In some places where have the special demands for control mode and the speed of frequency change,DDS based on FPGA is the best chioce.In this paper,we reduce the space of ROM to 50% and by replacing the phase accumulator which is the core component of DDS with whirl phase accumulator,and hike the frequency resolution ratio to 200%.In addition,the mixed simulation environment which is compounded of Quartus II,VC and Labwindows/CVI makes the design avoid limited by the hardware and raise the successful probability of implementation on hardware.更多还原