【摘要】 介绍2-1级联的三阶调制器设计结构,讨论信号比例系数、积分增益系数和电路非理想特性对调制器系统的性能影响;运用SIMULINK对调制器建模并仿真,模型中考虑开关电容积分器的非理想因素对整个调制器的影响,并通过调整信号比例和积分增益系数来确定调制器性能和电路要求。当采样率为125和时钟频率2.50MHz时,该模型结构得到93dB的信噪失真比,可应用于实际的电路系统。更多还原

【Abstract】 This paper describes the architecture techniques which can be employed to enhance the system-level modulator performance. The 2-1 cascaded architecture used in this design is presented, along with a discussion on the integrator gain factors and a consideration of the circuit non-idealities, including signal scaling and capacitor scaling, which affect its performance. With an oversampling ratio of 125 and a clock frequency of 2.5MHz, the modulator achieves a 90dB dynamic range and a peak signal-to-noise distortion ratio (SNDR) of 93dB.更多还原