【摘要】 本文用Verilog硬件描述语言设计了一个完整的直序扩频通信系统。其中扩频编码采用M序列,接收端同步捕获过程利用数字匹配滤波器的原理。在设计过程中对扩频码调制、同步头序列载入进行了技巧性设计,同时考虑了同步解扩后的去噪音处理。本文为设计直序扩频通信系统提供了参考模型。更多还原

【Abstract】 This article is focused on the implement of an integrated Direct Sequence Spread Spectrum Communications System byVerilog HDL. The designer adopted M-sequence to modulate the original signals, and used the method of Digital Match Filer to capture the synchronous process. Especially, the designer found a skillful method to implement the modulation of pseudo codes and theloadings of synchronous head signals. Noise disturbance and solutions were even considered. This article is a basic reference of modelfor designing the DSSS.更多还原