【摘要】 本文介绍一种用于高性能DSP的32位浮点乘法器设计,通过采用改进Booth编码的树状4-2压缩器结构,提高了速度,降低了功耗,该乘法器结构规则且适合于VLSI实现,单个周期内完成一次24位整数乘或者32位浮点乘。整个设计采用Verilog HDL语言结构级描述,用0.25um单元库进行逻辑综合.完成一次乘法运算时间为24.30ns.更多还原

【Abstract】 The paper explores a design for 32-bit floating-point multipliers,which is used in high performances DSP chips.By using a structure of 4-2 column compression tree with the modified Booth encoding,the speed of the multipliers is improved and the pow-er of the system is reduced.Furthermore,due to a more regular structure adopted,it is easy for VLSI realization of the multipliers.The algorithm has been implemented in a 32-bit floating-point array multiplier,which performs single-cycle multiplication on 24-bit integer or 32-bit floating-point values.The whole design is described in Verilog DHL at structure level,and synthesized using the 0.25um standard cell library.It spends 24.30ns completing a 32-bit floating-point multiplication.更多还原