【摘要】 随着数字逻辑设计越来越复杂,验证的难度也越来越大。根据一款以太网交换芯片的项目完成所总结的经验,提出了一种基于Vera的电路行为级建模的验证方法。实验结果表明,这种验证方法可以方便地进行RTL和参考模型的联合仿真,并能最大限度地提高验证覆盖率,有效地减少验证工作量和缩短验证时间。更多还原

【Abstract】 Along with the increment of complexity in digital ASIC design,there are more and more difficulties in verification of the HDL design.According to a kind of Ethernet exchange chip program,gives a modeling verification method,which is based on OpenVera language.It has been proved that this method can make the combined simulation of RTL and reference model conveniently,improve the recovery rate,reduce the task and shorten the time of test and verify effectively.更多还原