【摘要】 采用高速鉴频鉴相器、抗抖动电荷泵和差分对称负载延迟单元优化结构,综合分析环形振荡器各类噪声模型,设计了一种适用于HDTV的低抖动时钟电路。芯片采用SMIC 0.35μm标准CMOS工艺,3.3 V电源电压。在一定测试环境下,输出30 MHz时钟信号抖动σ仅为10.4 ps,能很好地满足电路设计要求。更多还原

【Abstract】 A low-jitter clock generator for HDTV is designed with a high-speed phase/frequency detector,a noise-suppressed charge pump and symmetrical load differential delay cells.Different noise models of the ring oscillator are discussed.Implemented in SMIC’s 0.35 μm standard CMOS process,the circuit operates at 3.3 V power supply.Under certain testing circumstance,clock jitter of the voltage controlled oscillator for 30 MHz output is 10.4 ps,which meets the specification well.更多还原