【摘要】 提出了一种采用片内PLL实现实速扫描测试的方案.在该方案中,移入测试向量时使用测试仪提供的时钟,激励施加和响应捕获采用片内PLL生成的高速时钟,降低了实速扫描测试对测试仪时钟频率的要求.在AC’97音频控制器电路上进行的实验,证实了该方案的可行性.更多还原

【Abstract】 At-speed test,which is efficient in detecting timing related faults,has been widely used in VLSI test.For at-speed test,one key issue is how to generate test clock at system speed.This paper presents an on-chip PLL(phase-locked-loop)based at-speed scan test scheme.In this method,an ATE(automation test equipment)clock is used during shift phase.On-chip PLL is used to generate at-speed clock during launch and capture phase.Therefore,at-speed scan test can be conducted with a low speed ATE.Experimental results on an AC’97 controller circuit have verified the effectiveness of the proposed scheme.更多还原